From 65d7f52098f062c372546170b4e355edbc264584 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Tue, 9 Mar 2021 09:44:02 -0800 Subject: [PATCH] intel: Fix broken alignment due to gen_ prefix renaming Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke Part-of: --- src/gallium/drivers/iris/iris_batch.c | 8 +++--- src/gallium/drivers/iris/iris_bufmgr.c | 6 ++-- src/gallium/drivers/iris/iris_resource.c | 4 +-- src/gallium/drivers/iris/iris_state.c | 22 +++++++------- src/intel/blorp/blorp_genX_exec.h | 6 ++-- src/intel/common/intel_aux_map.c | 18 ++++++------ src/intel/common/intel_aux_map.h | 18 ++++++------ src/intel/common/intel_batch_decoder.c | 24 ++++++++-------- src/intel/common/intel_decoder.c | 18 ++++++------ src/intel/common/intel_decoder.h | 41 +++++++++++++-------------- src/intel/common/intel_disasm.c | 4 +-- src/intel/common/intel_disasm.h | 2 +- src/intel/common/intel_guardband.h | 6 ++-- src/intel/common/intel_l3_config.c | 6 ++-- src/intel/common/intel_l3_config.h | 18 ++++++------ src/intel/common/intel_urb_config.c | 12 ++++---- src/intel/common/intel_uuid.c | 8 +++--- src/intel/common/intel_uuid.h | 8 +++--- src/intel/tools/aub_read.c | 2 +- src/intel/tools/aubinator.c | 4 +-- src/intel/tools/aubinator_error_decode.c | 8 +++--- src/intel/tools/aubinator_viewer.cpp | 4 +-- src/intel/tools/aubinator_viewer_decoder.cpp | 4 +-- src/intel/vulkan/anv_allocator.c | 10 +++---- src/intel/vulkan/anv_batch_chain.c | 16 +++++------ src/intel/vulkan/anv_device.c | 8 +++--- src/intel/vulkan/anv_perf.c | 2 +- src/intel/vulkan/anv_pipeline.c | 2 +- src/intel/vulkan/anv_private.h | 8 +++--- src/intel/vulkan/gen8_cmd_buffer.c | 16 +++++------ src/intel/vulkan/genX_cmd_buffer.c | 2 +- src/intel/vulkan/genX_pipeline.c | 10 +++---- src/intel/vulkan/genX_query.c | 8 +++--- src/mesa/drivers/dri/i965/gen7_l3_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_urb.c | 4 +-- src/mesa/drivers/dri/i965/genX_state_upload.c | 10 +++---- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 +++--- 37 files changed, 178 insertions(+), 179 deletions(-) diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c index ac38cbc..1eafb61 100644 --- a/src/gallium/drivers/iris/iris_batch.c +++ b/src/gallium/drivers/iris/iris_batch.c @@ -164,7 +164,7 @@ decode_batch(struct iris_batch *batch) { void *map = iris_bo_map(batch->dbg, batch->exec_bos[0], MAP_READ); intel_print_batch(&batch->decoder, map, batch->primary_batch_size, - batch->exec_bos[0]->gtt_offset, false); + batch->exec_bos[0]->gtt_offset, false); } void @@ -221,8 +221,8 @@ iris_init_batch(struct iris_context *ice, GEN_BATCH_DECODE_FLOATS; intel_batch_decode_ctx_init(&batch->decoder, &screen->devinfo, - stderr, decode_flags, NULL, - decode_get_bo, decode_get_state_size, batch); + stderr, decode_flags, NULL, + decode_get_bo, decode_get_state_size, batch); batch->decoder.dynamic_base = IRIS_MEMZONE_DYNAMIC_START; batch->decoder.instruction_base = IRIS_MEMZONE_SHADER_START; batch->decoder.max_vbo_decoded_lines = 32; @@ -510,7 +510,7 @@ add_aux_map_bos_to_batch(struct iris_batch *batch) uint32_t count = intel_aux_map_get_num_buffers(aux_map_ctx); ensure_exec_obj_space(batch, count); intel_aux_map_fill_bos(aux_map_ctx, - (void**)&batch->exec_bos[batch->exec_count], count); + (void**)&batch->exec_bos[batch->exec_count], count); for (uint32_t i = 0; i < count; i++) { struct iris_bo *bo = batch->exec_bos[batch->exec_count]; iris_bo_reference(bo); diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index 5e65ce5..ce18883 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -430,7 +430,7 @@ alloc_bo_from_cache(struct iris_bufmgr *bufmgr, */ if (bo->bufmgr->aux_map_ctx) intel_aux_map_unmap_range(bo->bufmgr->aux_map_ctx, bo->gtt_offset, - bo->size); + bo->size); bo->aux_map_address = 0; } @@ -781,7 +781,7 @@ bo_close(struct iris_bo *bo) if (bo->aux_map_address && bo->bufmgr->aux_map_ctx) { intel_aux_map_unmap_range(bo->bufmgr->aux_map_ctx, bo->gtt_offset, - bo->size); + bo->size); } /* Return the VMA for reuse */ @@ -1887,7 +1887,7 @@ iris_bufmgr_create(struct gen_device_info *devinfo, int fd, bool bo_reuse) if (devinfo->has_aux_map) { bufmgr->aux_map_ctx = intel_aux_map_init(bufmgr, &aux_map_allocator, - devinfo); + devinfo); assert(bufmgr->aux_map_ctx); } diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index a7fc9d3..ac111eb 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -497,8 +497,8 @@ map_aux_addresses(struct iris_screen *screen, struct iris_resource *res, const uint64_t format_bits = intel_aux_map_format_bits(res->surf.tiling, format, plane); intel_aux_map_add_mapping(aux_map_ctx, res->bo->gtt_offset + res->offset, - res->aux.bo->gtt_offset + aux_offset, - res->surf.size_B, format_bits); + res->aux.bo->gtt_offset + aux_offset, + res->surf.size_B, format_bits); res->bo->aux_map_address = res->aux.bo->gtt_offset; } } diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 39a731b..f2a0c69 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -5641,9 +5641,9 @@ iris_upload_dirty_render_state(struct iris_context *ice, float vp_ymax = viewport_extent(state, 1, 1.0f); intel_calculate_guardband_size(cso_fb->width, cso_fb->height, - state->scale[0], state->scale[1], - state->translate[0], state->translate[1], - &gb_xmin, &gb_xmax, &gb_ymin, &gb_ymax); + state->scale[0], state->scale[1], + state->translate[0], state->translate[1], + &gb_xmin, &gb_xmax, &gb_ymin, &gb_ymax); iris_pack_state(GENX(SF_CLIP_VIEWPORT), vp_map, vp) { vp.ViewportMatrixElementm00 = state->scale[0]; @@ -5683,14 +5683,14 @@ iris_upload_dirty_render_state(struct iris_context *ice, } intel_get_urb_config(&batch->screen->devinfo, - batch->screen->l3_config_3d, - ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL, - ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL, - ice->shaders.urb.size, - ice->shaders.urb.entries, - ice->shaders.urb.start, - &ice->state.urb_deref_block_size, - &ice->shaders.urb.constrained); + batch->screen->l3_config_3d, + ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL, + ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL, + ice->shaders.urb.size, + ice->shaders.urb.entries, + ice->shaders.urb.start, + &ice->state.urb_deref_block_size, + &ice->shaders.urb.constrained); for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) { diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index a19a3d9..e379b5c 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -223,9 +223,9 @@ emit_urb_config(struct blorp_batch *batch, unsigned entries[4], start[4]; bool constrained; intel_get_urb_config(batch->blorp->compiler->devinfo, - blorp_get_l3_config(batch), - false, false, entry_size, - entries, start, deref_block_size, &constrained); + blorp_get_l3_config(batch), + false, false, entry_size, + entries, start, deref_block_size, &constrained); #if GEN_GEN == 7 && !GEN_IS_HASWELL /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: diff --git a/src/intel/common/intel_aux_map.c b/src/intel/common/intel_aux_map.c index 2f1cf45..8560d15 100644 --- a/src/intel/common/intel_aux_map.c +++ b/src/intel/common/intel_aux_map.c @@ -199,8 +199,8 @@ intel_aux_map_get_state_num(struct intel_aux_map_context *ctx) struct intel_aux_map_context * intel_aux_map_init(void *driver_ctx, - struct gen_mapped_pinned_buffer_alloc *buffer_alloc, - const struct gen_device_info *devinfo) + struct gen_mapped_pinned_buffer_alloc *buffer_alloc, + const struct gen_device_info *devinfo) { struct intel_aux_map_context *ctx; if (devinfo->gen < 12) @@ -314,7 +314,7 @@ get_bpp_encoding(enum isl_format format) uint64_t intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format, - uint8_t plane) + uint8_t plane) { if (aux_map_debug) fprintf(stderr, "AUX-MAP entry %s, bpp_enc=%d\n", @@ -434,8 +434,8 @@ add_mapping(struct intel_aux_map_context *ctx, uint64_t address, uint64_t * intel_aux_map_get_entry(struct intel_aux_map_context *ctx, - uint64_t address, - uint64_t *entry_address) + uint64_t address, + uint64_t *entry_address) { pthread_mutex_lock(&ctx->mutex); uint64_t *l1_entry_map; @@ -447,8 +447,8 @@ intel_aux_map_get_entry(struct intel_aux_map_context *ctx, void intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t address, - uint64_t aux_address, uint64_t main_size_B, - uint64_t format_bits) + uint64_t aux_address, uint64_t main_size_B, + uint64_t format_bits) { bool state_changed = false; pthread_mutex_lock(&ctx->mutex); @@ -521,7 +521,7 @@ remove_mapping(struct intel_aux_map_context *ctx, uint64_t address, void intel_aux_map_unmap_range(struct intel_aux_map_context *ctx, uint64_t address, - uint64_t size) + uint64_t size) { bool state_changed = false; pthread_mutex_lock(&ctx->mutex); @@ -548,7 +548,7 @@ intel_aux_map_get_num_buffers(struct intel_aux_map_context *ctx) void intel_aux_map_fill_bos(struct intel_aux_map_context *ctx, void **driver_bos, - uint32_t max_bos) + uint32_t max_bos) { assert(p_atomic_read(&ctx->num_buffers) >= max_bos); uint32_t i = 0; diff --git a/src/intel/common/intel_aux_map.h b/src/intel/common/intel_aux_map.h index 4d9dc8c..7f58f30 100644 --- a/src/intel/common/intel_aux_map.h +++ b/src/intel/common/intel_aux_map.h @@ -53,8 +53,8 @@ struct gen_device_info; struct intel_aux_map_context * intel_aux_map_init(void *driver_ctx, - struct gen_mapped_pinned_buffer_alloc *buffer_alloc, - const struct gen_device_info *devinfo); + struct gen_mapped_pinned_buffer_alloc *buffer_alloc, + const struct gen_device_info *devinfo); void intel_aux_map_finish(struct intel_aux_map_context *ctx); @@ -79,31 +79,31 @@ intel_aux_map_get_num_buffers(struct intel_aux_map_context *ctx); */ void intel_aux_map_fill_bos(struct intel_aux_map_context *ctx, void **driver_bos, - uint32_t max_bos); + uint32_t max_bos); uint64_t intel_aux_map_get_base(struct intel_aux_map_context *ctx); uint64_t intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format, - uint8_t plane); + uint8_t plane); uint64_t intel_aux_map_format_bits_for_isl_surf(const struct isl_surf *isl_surf); uint64_t * intel_aux_map_get_entry(struct intel_aux_map_context *ctx, - uint64_t address, - uint64_t *entry_address); + uint64_t address, + uint64_t *entry_address); void intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t address, - uint64_t aux_address, uint64_t main_size_B, - uint64_t format_bits); + uint64_t aux_address, uint64_t main_size_B, + uint64_t format_bits); void intel_aux_map_unmap_range(struct intel_aux_map_context *ctx, uint64_t address, - uint64_t size); + uint64_t size); #ifdef __cplusplus } diff --git a/src/intel/common/intel_batch_decoder.c b/src/intel/common/intel_batch_decoder.c index b2929be..700e3fd 100644 --- a/src/intel/common/intel_batch_decoder.c +++ b/src/intel/common/intel_batch_decoder.c @@ -30,15 +30,15 @@ void intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx, - const struct gen_device_info *devinfo, - FILE *fp, enum intel_batch_decode_flags flags, - const char *xml_path, - struct intel_batch_decode_bo (*get_bo)(void *, - bool, - uint64_t), - unsigned (*get_state_size)(void *, uint64_t, - uint64_t), - void *user_data) + const struct gen_device_info *devinfo, + FILE *fp, enum intel_batch_decode_flags flags, + const char *xml_path, + struct intel_batch_decode_bo (*get_bo)(void *, + bool, + uint64_t), + unsigned (*get_state_size)(void *, uint64_t, + uint64_t), + void *user_data) { memset(ctx, 0, sizeof(*ctx)); @@ -1078,8 +1078,8 @@ struct custom_decoder { void intel_print_batch(struct intel_batch_decode_ctx *ctx, - const uint32_t *batch, uint32_t batch_size, - uint64_t batch_addr, bool from_ring) + const uint32_t *batch, uint32_t batch_size, + uint64_t batch_addr, bool from_ring) { const uint32_t *p, *end = batch + batch_size / sizeof(uint32_t); int length; @@ -1181,7 +1181,7 @@ intel_print_batch(struct intel_batch_decode_ctx *ctx, next_batch_addr); } else { intel_print_batch(ctx, next_batch.map, next_batch.size, - next_batch.addr, false); + next_batch.addr, false); } if (second_level) { /* MI_BATCH_BUFFER_START with "2nd Level Batch Buffer" set acts diff --git a/src/intel/common/intel_decoder.c b/src/intel/common/intel_decoder.c index 155cd67..1dab245 100644 --- a/src/intel/common/intel_decoder.c +++ b/src/intel/common/intel_decoder.c @@ -736,7 +736,7 @@ intel_spec_load_filename(const char *filename) struct intel_spec * intel_spec_load_from_path(const struct gen_device_info *devinfo, - const char *path) + const char *path) { size_t filename_len = strlen(path) + 20; char *filename = malloc(filename_len); @@ -758,8 +758,8 @@ void intel_spec_destroy(struct intel_spec *spec) struct intel_group * intel_spec_find_instruction(struct intel_spec *spec, - enum drm_i915_gem_engine_class engine, - const uint32_t *p) + enum drm_i915_gem_engine_class engine, + const uint32_t *p) { hash_table_foreach(spec->commands, entry) { struct intel_group *command = entry->data; @@ -1092,7 +1092,7 @@ iter_decode_field(struct intel_field_iterator *iter) iter->field->type.intel_struct->name); iter->struct_desc = intel_spec_find_struct(iter->group->spec, - iter->field->type.intel_struct->name); + iter->field->type.intel_struct->name); break; case GEN_TYPE_UFIXED: snprintf(iter->value, sizeof(iter->value), "%f", @@ -1149,9 +1149,9 @@ iter_decode_field(struct intel_field_iterator *iter) void intel_field_iterator_init(struct intel_field_iterator *iter, - struct intel_group *group, - const uint32_t *p, int p_bit, - bool print_colors) + struct intel_group *group, + const uint32_t *p, int p_bit, + bool print_colors) { memset(iter, 0, sizeof(*iter)); @@ -1221,7 +1221,7 @@ intel_field_is_header(struct intel_field *field) void intel_print_group(FILE *outfile, struct intel_group *group, uint64_t offset, - const uint32_t *p, int p_bit, bool color) + const uint32_t *p, int p_bit, bool color) { struct intel_field_iterator iter; int last_dword = -1; @@ -1240,7 +1240,7 @@ intel_print_group(FILE *outfile, struct intel_group *group, uint64_t offset, int struct_dword = iter.start_bit / 32; uint64_t struct_offset = offset + 4 * struct_dword; intel_print_group(outfile, iter.struct_desc, struct_offset, - &p[struct_dword], iter.start_bit % 32, color); + &p[struct_dword], iter.start_bit % 32, color); } } } diff --git a/src/intel/common/intel_decoder.h b/src/intel/common/intel_decoder.h index 3f96ac2..720e18f 100644 --- a/src/intel/common/intel_decoder.h +++ b/src/intel/common/intel_decoder.h @@ -53,13 +53,13 @@ static inline uint32_t intel_make_gen(uint32_t major, uint32_t minor) struct intel_group *intel_spec_find_struct(struct intel_spec *spec, const char *name); struct intel_spec *intel_spec_load(const struct gen_device_info *devinfo); struct intel_spec *intel_spec_load_from_path(const struct gen_device_info *devinfo, - const char *path); + const char *path); struct intel_spec *intel_spec_load_filename(const char *filename); void intel_spec_destroy(struct intel_spec *spec); uint32_t intel_spec_get_gen(struct intel_spec *spec); struct intel_group *intel_spec_find_instruction(struct intel_spec *spec, - enum drm_i915_gem_engine_class engine, - const uint32_t *p); + enum drm_i915_gem_engine_class engine, + const uint32_t *p); struct intel_group *intel_spec_find_register(struct intel_spec *spec, uint32_t offset); struct intel_group *intel_spec_find_register_by_name(struct intel_spec *spec, const char *name); struct intel_enum *intel_spec_find_enum(struct intel_spec *spec, const char *name); @@ -194,16 +194,16 @@ struct intel_field { }; void intel_field_iterator_init(struct intel_field_iterator *iter, - struct intel_group *group, - const uint32_t *p, int p_bit, - bool print_colors); + struct intel_group *group, + const uint32_t *p, int p_bit, + bool print_colors); bool intel_field_iterator_next(struct intel_field_iterator *iter); void intel_print_group(FILE *out, - struct intel_group *group, - uint64_t offset, const uint32_t *p, int p_bit, - bool color); + struct intel_group *group, + uint64_t offset, const uint32_t *p, int p_bit, + bool color); enum intel_batch_decode_flags { /** Print in color! */ @@ -252,22 +252,21 @@ struct intel_batch_decode_ctx { }; void intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx, - const struct gen_device_info *devinfo, - FILE *fp, enum intel_batch_decode_flags flags, - const char *xml_path, - struct intel_batch_decode_bo (*get_bo)(void *, - bool, - uint64_t), - - unsigned (*get_state_size)(void *, uint64_t, - uint64_t), - void *user_data); + const struct gen_device_info *devinfo, + FILE *fp, enum intel_batch_decode_flags flags, + const char *xml_path, + struct intel_batch_decode_bo (*get_bo)(void *, + bool, + uint64_t), + unsigned (*get_state_size)(void *, uint64_t, + uint64_t), + void *user_data); void intel_batch_decode_ctx_finish(struct intel_batch_decode_ctx *ctx); void intel_print_batch(struct intel_batch_decode_ctx *ctx, - const uint32_t *batch, uint32_t batch_size, - uint64_t batch_addr, bool from_ring); + const uint32_t *batch, uint32_t batch_size, + uint64_t batch_addr, bool from_ring); #ifdef __cplusplus } diff --git a/src/intel/common/intel_disasm.c b/src/intel/common/intel_disasm.c index 2d0cbab..310ae33 100644 --- a/src/intel/common/intel_disasm.c +++ b/src/intel/common/intel_disasm.c @@ -39,7 +39,7 @@ is_send(uint32_t opcode) static int intel_disasm_find_end(const struct gen_device_info *devinfo, - const void *assembly, int start) + const void *assembly, int start) { int offset = start; @@ -65,7 +65,7 @@ intel_disasm_find_end(const struct gen_device_info *devinfo, void intel_disassemble(const struct gen_device_info *devinfo, - const void *assembly, int start, FILE *out) + const void *assembly, int start, FILE *out) { int end = intel_disasm_find_end(devinfo, assembly, start); diff --git a/src/intel/common/intel_disasm.h b/src/intel/common/intel_disasm.h index 0d36640..b2bed3a 100644 --- a/src/intel/common/intel_disasm.h +++ b/src/intel/common/intel_disasm.h @@ -31,7 +31,7 @@ extern "C" { #endif void intel_disassemble(const struct gen_device_info *devinfo, - const void *assembly, int start, FILE *out); + const void *assembly, int start, FILE *out); #ifdef __cplusplus } diff --git a/src/intel/common/intel_guardband.h b/src/intel/common/intel_guardband.h index b141f65..e1a1fb5 100644 --- a/src/intel/common/intel_guardband.h +++ b/src/intel/common/intel_guardband.h @@ -25,9 +25,9 @@ static inline void intel_calculate_guardband_size(uint32_t fb_width, uint32_t fb_height, - float m00, float m11, float m30, float m31, - float *xmin, float *xmax, - float *ymin, float *ymax) + float m00, float m11, float m30, float m31, + float *xmin, float *xmax, + float *ymin, float *ymax) { /* According to the "Vertex X,Y Clamping and Quantization" section of the * Strips and Fans documentation: diff --git a/src/intel/common/intel_l3_config.c b/src/intel/common/intel_l3_config.c index 00ac09b..3ea90b1 100644 --- a/src/intel/common/intel_l3_config.c +++ b/src/intel/common/intel_l3_config.c @@ -258,7 +258,7 @@ intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1) */ struct intel_l3_weights intel_get_default_l3_weights(const struct gen_device_info *devinfo, - bool needs_dc, bool needs_slm) + bool needs_dc, bool needs_slm) { struct intel_l3_weights w = {{ 0 }}; @@ -302,7 +302,7 @@ intel_get_default_l3_config(const struct gen_device_info *devinfo) */ const struct intel_l3_config * intel_get_l3_config(const struct gen_device_info *devinfo, - struct intel_l3_weights w0) + struct intel_l3_weights w0) { const struct intel_l3_list *const list = get_l3_list(devinfo); const struct intel_l3_config *const cfgs = list->configs; @@ -349,7 +349,7 @@ get_urb_size_scale(const struct gen_device_info *devinfo) unsigned intel_get_l3_config_urb_size(const struct gen_device_info *devinfo, - const struct intel_l3_config *cfg) + const struct intel_l3_config *cfg) { /* We don't have to program the URB size in DG1, it's a fixed value. */ if (devinfo->is_dg1) diff --git a/src/intel/common/intel_l3_config.h b/src/intel/common/intel_l3_config.h index 862e8a0..2a26bfe 100644 --- a/src/intel/common/intel_l3_config.h +++ b/src/intel/common/intel_l3_config.h @@ -74,7 +74,7 @@ float intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights struct intel_l3_weights intel_get_default_l3_weights(const struct gen_device_info *devinfo, - bool needs_dc, bool needs_slm); + bool needs_dc, bool needs_slm); struct intel_l3_weights intel_get_l3_config_weights(const struct intel_l3_config *cfg); @@ -84,11 +84,11 @@ intel_get_default_l3_config(const struct gen_device_info *devinfo); const struct intel_l3_config * intel_get_l3_config(const struct gen_device_info *devinfo, - struct intel_l3_weights w0); + struct intel_l3_weights w0); unsigned intel_get_l3_config_urb_size(const struct gen_device_info *devinfo, - const struct intel_l3_config *cfg); + const struct intel_l3_config *cfg); void intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp); @@ -99,11 +99,11 @@ enum intel_urb_deref_block_size { }; void intel_get_urb_config(const struct gen_device_info *devinfo, - const struct intel_l3_config *l3_cfg, - bool tess_present, bool gs_present, - const unsigned entry_size[4], - unsigned entries[4], unsigned start[4], - enum intel_urb_deref_block_size *deref_block_size, - bool *constrained); + const struct intel_l3_config *l3_cfg, + bool tess_present, bool gs_present, + const unsigned entry_size[4], + unsigned entries[4], unsigned start[4], + enum intel_urb_deref_block_size *deref_block_size, + bool *constrained); #endif /* INTEL_L3_CONFIG_H */ diff --git a/src/intel/common/intel_urb_config.c b/src/intel/common/intel_urb_config.c index fdf8199..97ce4e8 100644 --- a/src/intel/common/intel_urb_config.c +++ b/src/intel/common/intel_urb_config.c @@ -61,12 +61,12 @@ */ void intel_get_urb_config(const struct gen_device_info *devinfo, - const struct intel_l3_config *l3_cfg, - bool tess_present, bool gs_present, - const unsigned entry_size[4], - unsigned entries[4], unsigned start[4], - enum intel_urb_deref_block_size *deref_block_size, - bool *constrained) + const struct intel_l3_config *l3_cfg, + bool tess_present, bool gs_present, + const unsigned entry_size[4], + unsigned entries[4], unsigned start[4], + enum intel_urb_deref_block_size *deref_block_size, + bool *constrained) { unsigned urb_size_kB = intel_get_l3_config_urb_size(devinfo, l3_cfg); diff --git a/src/intel/common/intel_uuid.c b/src/intel/common/intel_uuid.c index 8e98ddf..f531ce5 100644 --- a/src/intel/common/intel_uuid.c +++ b/src/intel/common/intel_uuid.c @@ -27,8 +27,8 @@ void intel_uuid_compute_device_id(uint8_t *uuid, - const struct isl_device *isldev, - size_t size) + const struct isl_device *isldev, + size_t size) { struct mesa_sha1 sha1_ctx; uint8_t sha1[20]; @@ -53,8 +53,8 @@ intel_uuid_compute_device_id(uint8_t *uuid, void intel_uuid_compute_driver_id(uint8_t *uuid, - const struct gen_device_info *devinfo, - size_t size) + const struct gen_device_info *devinfo, + size_t size) { const char* intelDriver = PACKAGE_VERSION MESA_GIT_SHA1; struct mesa_sha1 sha1_ctx; diff --git a/src/intel/common/intel_uuid.h b/src/intel/common/intel_uuid.h index b654a88..53336b3 100644 --- a/src/intel/common/intel_uuid.h +++ b/src/intel/common/intel_uuid.h @@ -33,12 +33,12 @@ extern "C" { #endif void intel_uuid_compute_device_id(uint8_t *uuid, - const struct isl_device *isldev, - size_t size); + const struct isl_device *isldev, + size_t size); void intel_uuid_compute_driver_id(uint8_t *uuid, - const struct gen_device_info *devinfo, - size_t size); + const struct gen_device_info *devinfo, + size_t size); #ifdef __cplusplus } diff --git a/src/intel/tools/aub_read.c b/src/intel/tools/aub_read.c index 6dd4032..0724aab 100644 --- a/src/intel/tools/aub_read.c +++ b/src/intel/tools/aub_read.c @@ -140,7 +140,7 @@ handle_trace_block(struct aub_read *read, const uint32_t *p) enum drm_i915_gem_engine_class engine = I915_ENGINE_CLASS_RENDER; const void *data = p + header_length + 2; uint64_t address = intel_48b_address((read->devinfo.gen >= 8 ? ((uint64_t) p[5] << 32) : 0) | - ((uint64_t) p[3])); + ((uint64_t) p[3])); uint32_t size = p[4]; switch (operation) { diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c index 53cecb8..b7f94a4 100644 --- a/src/intel/tools/aubinator.c +++ b/src/intel/tools/aubinator.c @@ -93,7 +93,7 @@ aubinator_init(void *user_data, int aub_pci_id, const char *app_name) batch_flags |= GEN_BATCH_DECODE_FLOATS; intel_batch_decode_ctx_init(&batch_ctx, &devinfo, outfile, batch_flags, - xml_path, NULL, NULL, NULL); + xml_path, NULL, NULL, NULL); /* Check for valid spec instance, if wrong xml_path is passed then spec * instance is not initialized properly @@ -157,7 +157,7 @@ handle_execlist_write(void *user_data, enum drm_i915_gem_engine_class engine, ui batch_ctx.user_data = &mem; struct intel_batch_decode_bo ring_bo = aub_mem_get_ggtt_bo(&mem, - ring_buffer_start); + ring_buffer_start); assert(ring_bo.size > 0); void *commands = (uint8_t *)ring_bo.map + (ring_buffer_start - ring_bo.addr) + ring_buffer_head; diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c index 908d2e4..62e8a88 100644 --- a/src/intel/tools/aubinator_error_decode.c +++ b/src/intel/tools/aubinator_error_decode.c @@ -72,7 +72,7 @@ print_register(struct intel_spec *spec, const char *name, uint32_t reg) if (reg_spec) { intel_print_group(stdout, reg_spec, 0, ®, 0, - option_color == COLOR_ALWAYS); + option_color == COLOR_ALWAYS); } } @@ -663,7 +663,7 @@ read_data_file(FILE *file) struct intel_batch_decode_ctx batch_ctx; intel_batch_decode_ctx_init(&batch_ctx, &devinfo, stdout, batch_flags, - xml_path, get_gen_batch_bo, NULL, NULL); + xml_path, get_gen_batch_bo, NULL, NULL); for (int s = 0; s < num_sections; s++) { @@ -685,8 +685,8 @@ read_data_file(FILE *file) uint8_t *data = (uint8_t *)sections[s].data + sections[s].data_offset; uint64_t batch_addr = sections[s].gtt_offset + sections[s].data_offset; intel_print_batch(&batch_ctx, (uint32_t *)data, - sections[s].dword_count * 4, batch_addr, - is_ring_buffer); + sections[s].dword_count * 4, batch_addr, + is_ring_buffer); batch_ctx.flags = batch_flags; } } diff --git a/src/intel/tools/aubinator_viewer.cpp b/src/intel/tools/aubinator_viewer.cpp index de8a255..cb67ab6 100644 --- a/src/intel/tools/aubinator_viewer.cpp +++ b/src/intel/tools/aubinator_viewer.cpp @@ -393,8 +393,8 @@ new_shader_window(struct aub_mem *mem, uint64_t address, const char *desc) FILE *f = open_memstream(&window->shader, &window->shader_size); if (f) { intel_disassemble(&context.file->devinfo, - (const uint8_t *) shader_bo.map + - (address - shader_bo.addr), 0, f); + (const uint8_t *) shader_bo.map + + (address - shader_bo.addr), 0, f); fclose(f); } } diff --git a/src/intel/tools/aubinator_viewer_decoder.cpp b/src/intel/tools/aubinator_viewer_decoder.cpp index dc778da..234ce33 100644 --- a/src/intel/tools/aubinator_viewer_decoder.cpp +++ b/src/intel/tools/aubinator_viewer_decoder.cpp @@ -563,7 +563,7 @@ decode_3dstate_constant(struct aub_viewer_decode_ctx *ctx, struct intel_field_iterator iter; intel_field_iterator_init(&iter, body, &outer.p[outer.start_bit / 32], - 0, false); + 0, false); while (intel_field_iterator_next(&iter)) { int idx; @@ -815,7 +815,7 @@ handle_urb_constant(struct aub_viewer_decode_ctx *ctx, struct intel_field_iterator iter; intel_field_iterator_init(&iter, body, &outer.p[outer.start_bit / 32], - 0, false); + 0, false); ctx->urb_stages[ctx->stage].const_rd_length = 0; while (intel_field_iterator_next(&iter)) { diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c index 18cd038..6f71458 100644 --- a/src/intel/vulkan/anv_allocator.c +++ b/src/intel/vulkan/anv_allocator.c @@ -1714,9 +1714,9 @@ anv_device_alloc_bo(struct anv_device *device, if (new_bo._ccs_size > 0) { assert(device->info.has_aux_map); intel_aux_map_add_mapping(device->aux_map_ctx, - intel_canonical_address(new_bo.offset), - intel_canonical_address(new_bo.offset + new_bo.size), - new_bo.size, 0 /* format_bits */); + intel_canonical_address(new_bo.offset), + intel_canonical_address(new_bo.offset + new_bo.size), + new_bo.size, 0 /* format_bits */); } assert(new_bo.gem_handle); @@ -2036,8 +2036,8 @@ anv_device_release_bo(struct anv_device *device, assert(device->info.has_aux_map); assert(bo->has_implicit_ccs); intel_aux_map_unmap_range(device->aux_map_ctx, - intel_canonical_address(bo->offset), - bo->size); + intel_canonical_address(bo->offset), + bo->size); } if ((bo->flags & EXEC_OBJECT_PINNED) && !bo->has_fixed_address) diff --git a/src/intel/vulkan/anv_batch_chain.c b/src/intel/vulkan/anv_batch_chain.c index e6334e2..7977eb8 100644 --- a/src/intel/vulkan/anv_batch_chain.c +++ b/src/intel/vulkan/anv_batch_chain.c @@ -1932,8 +1932,8 @@ anv_queue_execbuf_locked(struct anv_queue *queue, submit->perf_query_pass); intel_print_batch(&device->decoder_ctx, - pass_batch_bo->map + pass_batch_offset, 64, - pass_batch_bo->offset + pass_batch_offset, false); + pass_batch_bo->map + pass_batch_offset, 64, + pass_batch_bo->offset + pass_batch_offset, false); } for (uint32_t i = 0; i < submit->cmd_buffer_count; i++) { @@ -1941,17 +1941,17 @@ anv_queue_execbuf_locked(struct anv_queue *queue, u_vector_tail(&submit->cmd_buffers[i]->seen_bbos); device->cmd_buffer_being_decoded = submit->cmd_buffers[i]; intel_print_batch(&device->decoder_ctx, (*bo)->bo->map, - (*bo)->bo->size, (*bo)->bo->offset, false); + (*bo)->bo->size, (*bo)->bo->offset, false); device->cmd_buffer_being_decoded = NULL; } } else if (submit->simple_bo) { intel_print_batch(&device->decoder_ctx, submit->simple_bo->map, - submit->simple_bo->size, submit->simple_bo->offset, false); + submit->simple_bo->size, submit->simple_bo->offset, false); } else { intel_print_batch(&device->decoder_ctx, - device->trivial_batch_bo->map, - device->trivial_batch_bo->size, - device->trivial_batch_bo->offset, false); + device->trivial_batch_bo->map, + device->trivial_batch_bo->size, + device->trivial_batch_bo->offset, false); } } @@ -1995,7 +1995,7 @@ anv_queue_execbuf_locked(struct anv_queue *queue, (query_info->kind == GEN_PERF_QUERY_TYPE_OA || query_info->kind == GEN_PERF_QUERY_TYPE_RAW)) { int ret = intel_ioctl(device->perf_fd, I915_PERF_IOCTL_CONFIG, - (void *)(uintptr_t) query_info->oa_metrics_set_id); + (void *)(uintptr_t) query_info->oa_metrics_set_id); if (ret < 0) { result = anv_device_set_lost(device, "i915-perf config failed: %s", diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index e84f094..4febdbb 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -2989,9 +2989,9 @@ VkResult anv_CreateDevice( GEN_BATCH_DECODE_FLOATS; intel_batch_decode_ctx_init(&device->decoder_ctx, - &physical_device->info, - stderr, decode_flags, NULL, - decode_get_bo, NULL, device); + &physical_device->info, + stderr, decode_flags, NULL, + decode_get_bo, NULL, device); } device->physical = physical_device; @@ -3205,7 +3205,7 @@ VkResult anv_CreateDevice( if (device->info.has_aux_map) { device->aux_map_ctx = intel_aux_map_init(device, &aux_map_allocator, - &physical_device->info); + &physical_device->info); if (!device->aux_map_ctx) goto fail_binding_table_pool; } diff --git a/src/intel/vulkan/anv_perf.c b/src/intel/vulkan/anv_perf.c index 04b173b..54e9208 100644 --- a/src/intel/vulkan/anv_perf.c +++ b/src/intel/vulkan/anv_perf.c @@ -284,7 +284,7 @@ VkResult anv_QueueSetPerformanceConfigurationINTEL( return VK_ERROR_INITIALIZATION_FAILED; } else { int ret = intel_ioctl(device->perf_fd, I915_PERF_IOCTL_CONFIG, - (void *)(uintptr_t) config->config_id); + (void *)(uintptr_t) config->config_id); if (ret < 0) return anv_device_set_lost(device, "i915-perf config failed: %m"); } diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 6f05ddc..af0dc6d 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1197,7 +1197,7 @@ anv_pipeline_add_executable(struct anv_pipeline *pipeline, * do it for every binary. */ intel_disassemble(&pipeline->device->info, - stage->code, code_offset, stream); + stage->code, code_offset, stream); fclose(stream); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 9266729..ee71d8d 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1242,7 +1242,7 @@ struct anv_device { int _lost; int lost_reported; - struct intel_batch_decode_ctx decoder_ctx; + struct intel_batch_decode_ctx decoder_ctx; /* * When decoding a anv_cmd_buffer, we might need to search for BOs through * the cmd_buffer's list. @@ -1252,7 +1252,7 @@ struct anv_device { int perf_fd; /* -1 if no opened */ uint64_t perf_metric; /* 0 if unset */ - struct intel_aux_map_context *aux_map_ctx; + struct intel_aux_map_context *aux_map_ctx; struct gen_debug_block_frame *debug_frame_desc; }; @@ -2784,7 +2784,7 @@ struct anv_cmd_compute_state { struct anv_cmd_state { /* PIPELINE_SELECT.PipelineSelection */ uint32_t current_pipeline; - const struct intel_l3_config * current_l3_config; + const struct intel_l3_config * current_l3_config; uint32_t last_aux_map_state; struct anv_cmd_graphics_state gfx; @@ -3331,7 +3331,7 @@ struct anv_pipeline { struct util_dynarray executables; - const struct intel_l3_config * l3_config; + const struct intel_l3_config * l3_config; }; struct anv_graphics_pipeline { diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c index 3f75ebc..b69fbed 100644 --- a/src/intel/vulkan/gen8_cmd_buffer.c +++ b/src/intel/vulkan/gen8_cmd_buffer.c @@ -72,14 +72,14 @@ gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) * fall back to a worst-case guardband of [-1, 1]. */ intel_calculate_guardband_size(fb->width, fb->height, - sfv.ViewportMatrixElementm00, - sfv.ViewportMatrixElementm11, - sfv.ViewportMatrixElementm30, - sfv.ViewportMatrixElementm31, - &sfv.XMinClipGuardband, - &sfv.XMaxClipGuardband, - &sfv.YMinClipGuardband, - &sfv.YMaxClipGuardband); + sfv.ViewportMatrixElementm00, + sfv.ViewportMatrixElementm11, + sfv.ViewportMatrixElementm30, + sfv.ViewportMatrixElementm31, + &sfv.XMinClipGuardband, + &sfv.XMaxClipGuardband, + &sfv.YMinClipGuardband, + &sfv.YMaxClipGuardband); } GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv); diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index ad98daf..d291bb5 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -528,7 +528,7 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer, uint64_t aux_entry_addr64, *aux_entry_map; aux_entry_map = intel_aux_map_get_entry(cmd_buffer->device->aux_map_ctx, - address, &aux_entry_addr64); + address, &aux_entry_addr64); assert(cmd_buffer->device->physical->use_softpin); struct anv_address aux_entry_address = { diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index cdcc6bc..86cbc7a 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -274,11 +274,11 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch, unsigned start[4]; bool constrained; intel_get_urb_config(devinfo, l3_config, - active_stages & - VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT, - active_stages & VK_SHADER_STAGE_GEOMETRY_BIT, - entry_size, entries, start, deref_block_size, - &constrained); + active_stages & + VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT, + active_stages & VK_SHADER_STAGE_GEOMETRY_BIT, + entry_size, entries, start, deref_block_size, + &constrained); #if GEN_GEN == 7 && !GEN_IS_HASWELL /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 7f4dfc4..32459f7 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -959,8 +959,8 @@ void genX(CmdBeginQueryIndexedEXT)( mi_iadd( &b, mi_imm(intel_canonical_address(pool->bo->offset + - khr_perf_query_data_offset(pool, query, 0, end) + - field->location)), + khr_perf_query_data_offset(pool, query, 0, end) + + field->location)), mi_reg64(ANV_PERF_QUERY_OFFSET_REG)); cmd_buffer->self_mod_locations[reloc_idx++] = mi_store_address(&b, reg_addr); @@ -970,8 +970,8 @@ void genX(CmdBeginQueryIndexedEXT)( mi_iadd( &b, mi_imm(intel_canonical_address(pool->bo->offset + - khr_perf_query_data_offset(pool, query, 0, end) + - field->location + 4)), + khr_perf_query_data_offset(pool, query, 0, end) + + field->location + 4)), mi_reg64(ANV_PERF_QUERY_OFFSET_REG)); cmd_buffer->self_mod_locations[reloc_idx++] = mi_store_address(&b, reg_addr); } diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index c0dacd2..915d5d7 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -61,7 +61,7 @@ get_pipeline_state_l3_weights(const struct brw_context *brw) } return intel_get_default_l3_weights(&brw->screen->devinfo, - needs_dc, needs_slm); + needs_dc, needs_slm); } /** diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 228731e..c945f83 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -249,8 +249,8 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, unsigned start[4]; bool constrained; intel_get_urb_config(devinfo, brw->l3.config, - tess_present, gs_present, entry_size, - entries, start, NULL, &constrained); + tess_present, gs_present, entry_size, + entries, start, NULL, &constrained); if (devinfo->gen == 7 && !devinfo->is_haswell && !devinfo->is_baytrail) gen7_emit_vs_workaround_flush(brw); diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 8b2289a..611a027 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -2464,11 +2464,11 @@ genX(upload_sf_clip_viewport)(struct brw_context *brw) sfv.ViewportMatrixElementm31 = translate[1] * y_scale + y_bias, sfv.ViewportMatrixElementm32 = translate[2], intel_calculate_guardband_size(fb_width, fb_height, - sfv.ViewportMatrixElementm00, - sfv.ViewportMatrixElementm11, - sfv.ViewportMatrixElementm30, - sfv.ViewportMatrixElementm31, - &gb_xmin, &gb_xmax, &gb_ymin, &gb_ymax); + sfv.ViewportMatrixElementm00, + sfv.ViewportMatrixElementm11, + sfv.ViewportMatrixElementm30, + sfv.ViewportMatrixElementm31, + &gb_xmin, &gb_xmax, &gb_ymin, &gb_ymax); clv.XMinClipGuardband = gb_xmin; diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index a80b119..49760e7 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -159,8 +159,8 @@ brw_batch_init(struct brw_context *brw) GEN_BATCH_DECODE_FLOATS; intel_batch_decode_ctx_init(&batch->decoder, devinfo, stderr, - decode_flags, NULL, decode_get_bo, - decode_get_state_size, brw); + decode_flags, NULL, decode_get_bo, + decode_get_state_size, brw); batch->decoder.max_vbo_decoded_lines = 100; } @@ -832,8 +832,8 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) if (INTEL_DEBUG & DEBUG_BATCH) { intel_print_batch(&batch->decoder, batch->batch.map, - 4 * USED_BATCH(*batch), - batch->batch.bo->gtt_offset, false); + 4 * USED_BATCH(*batch), + batch->batch.bo->gtt_offset, false); } if (brw->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB) -- 2.7.4