From 65b05ebdda18c1cebd88c72cc8f50530addb80c6 Mon Sep 17 00:00:00 2001 From: D Scott Phillips Date: Thu, 30 Apr 2020 23:12:07 +0000 Subject: [PATCH] anv,iris: Fix input vertex max for tcs on gen12 gen12 does away with the single patch dispatch mode for tcs, and increases some limits so that 8_patch mode can always work. Make the necessary changes so we don't try to fall back to single patch mode. Fixes KHR-GL46.tessellation_shader.single.max_patch_vertices and others Fixes: 44754279ace7 ("intel/fs/gen12: Use TCS 8_PATCH mode.") Reviewed-by: Kenneth Graunke Acked-by: Jason Ekstrand Part-of: --- src/gallium/drivers/iris/iris_state.c | 2 ++ src/intel/compiler/brw_vec4_tcs.cpp | 2 +- src/intel/genxml/gen12.xml | 2 +- src/intel/vulkan/genX_pipeline.c | 7 ++++++- 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 0d43412..a5b825f 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4178,6 +4178,8 @@ iris_store_tcs_state(struct iris_context *ice, * more than 2 times the number of instance count. */ assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances); + hs.DispatchGRFStartRegisterForURBData = prog_data->dispatch_grf_start_reg & 0x1f; + hs.DispatchGRFStartRegisterForURBData5 = prog_data->dispatch_grf_start_reg >> 5; #endif hs.InstanceCount = tcs_prog_data->instances - 1; diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 852c5a9..e9a6880 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -394,7 +394,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, if (compiler->use_tcs_8_patch && nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) && - 2 + has_primitive_id + key->input_vertices <= 31) { + 2 + has_primitive_id + key->input_vertices <= (devinfo->gen >= 12 ? 63 : 31)) { /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the * "Instance" field limits the number of output vertices to [1, 16] on * gen11 and below, or [1, 32] on gen12 and above. Secondly, the diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 9be40f6..3eebc30 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -1964,7 +1964,7 @@ - + diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index c6f4791..5277d22 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1624,7 +1624,12 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, hs.VertexURBEntryReadLength = 0; hs.VertexURBEntryReadOffset = 0; hs.DispatchGRFStartRegisterForURBData = - tcs_prog_data->base.base.dispatch_grf_start_reg; + tcs_prog_data->base.base.dispatch_grf_start_reg & 0x1f; +#if GEN_GEN >= 12 + hs.DispatchGRFStartRegisterForURBData5 = + tcs_prog_data->base.base.dispatch_grf_start_reg >> 5; +#endif + hs.PerThreadScratchSpace = get_scratch_space(tcs_bin); hs.ScratchSpaceBasePointer = -- 2.7.4