From 65710a7589e14e6676765c3c66a86b785b1867d1 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Wed, 7 Nov 2012 00:13:01 +0000 Subject: [PATCH] [arm fast-isel] Appease the machine verifier by using the proper register classes. For my test case the number of errors drop from 356 to 21. Part of rdar://12594152 llvm-svn: 167508 --- llvm/lib/Target/ARM/ARMFastISel.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 89b85d0..6611862 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -619,7 +619,10 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) { Reloc::Model RelocM = TM.getRelocationModel(); bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM); - unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); + const TargetRegisterClass *RC = isThumb2 ? + (const TargetRegisterClass*)&ARM::rGPRRegClass : + (const TargetRegisterClass*)&ARM::GPRRegClass; + unsigned DestReg = createResultReg(RC); // Use movw+movt when possible, it avoids constant pool entries. // Darwin targets don't support movt with Reloc::Static, see -- 2.7.4