From 651c36b5086db9038591bd1ac387dcb492d011f8 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 May 2020 20:12:11 -0400 Subject: [PATCH] AMDGPU: Select strict_fmul --- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 2 +- llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll | 178 ++++++++++++++++++++++++++++ llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll | 129 ++++++++++++++++++++ llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll | 96 +++++++++++++++ 5 files changed, 406 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll create mode 100644 llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll create mode 100644 llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index bff0510..174e725 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -470,7 +470,7 @@ defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>; defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>; defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">; defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>; -defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>; +defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>; defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>; defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN, AMDGPUmulhi_i24>; defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>; @@ -633,7 +633,7 @@ let FPDPRounding = 1 in { defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>; defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>; defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; -defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>; +defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>; let mayRaiseFPException = 0 in { def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index 225be74..47238c6 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -54,7 +54,7 @@ def V_PK_MAD_U16 : VOP3PInst<"v_pk_mad_u16", VOP3_Profile, any_fma>; def V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3_Profile, any_fadd>; -def V_PK_MUL_F16 : VOP3PInst<"v_pk_mul_f16", VOP3_Profile, fmul>; +def V_PK_MUL_F16 : VOP3PInst<"v_pk_mul_f16", VOP3_Profile, any_fmul>; } // End FPDPRounding = 1 def V_PK_MAX_F16 : VOP3PInst<"v_pk_max_f16", VOP3_Profile, fmaxnum_like>; def V_PK_MIN_F16 : VOP3PInst<"v_pk_min_f16", VOP3_Profile, fminnum_like>; diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll new file mode 100644 index 0000000..29cffeb --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll @@ -0,0 +1,178 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; FIXME: promotion not handled without f16 insts + +define half @v_constained_fmul_f16_fpexcept_strict(half %x, half %y) #0 { +; GCN-LABEL: v_constained_fmul_f16_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f16_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call half @llvm.experimental.constrained.fmul.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret half %val +} + +define half @v_constained_fmul_f16_fpexcept_ignore(half %x, half %y) #0 { +; GCN-LABEL: v_constained_fmul_f16_fpexcept_ignore: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f16_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call half @llvm.experimental.constrained.fmul.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.ignore") + ret half %val +} + +define half @v_constained_fmul_f16_fpexcept_maytrap(half %x, half %y) #0 { +; GCN-LABEL: v_constained_fmul_f16_fpexcept_maytrap: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f16_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call half @llvm.experimental.constrained.fmul.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap") + ret half %val +} + +define <2 x half> @v_constained_fmul_v2f16_fpexcept_strict(<2 x half> %x, <2 x half> %y) #0 { +; GFX9-LABEL: v_constained_fmul_v2f16_fpexcept_strict: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_strict: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <2 x half> %val +} + +define <2 x half> @v_constained_fmul_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 { +; GFX9-LABEL: v_constained_fmul_v2f16_fpexcept_ignore: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_ignore: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore") + ret <2 x half> %val +} + +define <2 x half> @v_constained_fmul_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 { +; GFX9-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap") + ret <2 x half> %val +} + +define <3 x half> @v_constained_fmul_v3f16_fpexcept_strict(<3 x half> %x, <3 x half> %y) #0 { +; GFX9-LABEL: v_constained_fmul_v3f16_fpexcept_strict: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2 +; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_constained_fmul_v3f16_fpexcept_strict: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3 +; GFX8-NEXT: s_setpc_b64 s[30:31] + %val = call <3 x half> @llvm.experimental.constrained.fmul.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <3 x half> %val +} + +; FIXME: Scalarized +define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 { +; GFX9-LABEL: v_constained_fmul_v4f16_fpexcept_strict: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v0, v0, v2 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff +; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3 +; GFX9-NEXT: v_and_b32_e32 v0, v2, v0 +; GFX9-NEXT: v_and_b32_e32 v1, v2, v1 +; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0 +; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_constained_fmul_v4f16_fpexcept_strict: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3 +; GFX8-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] + %val = call <4 x half> @llvm.experimental.constrained.fmul.v4f16(<4 x half> %x, <4 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <4 x half> %val +} + +define amdgpu_ps half @s_constained_fmul_f16_fpexcept_strict(half inreg %x, half inreg %y) #0 { +; GCN-LABEL: s_constained_fmul_f16_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, s3 +; GCN-NEXT: v_mul_f16_e32 v0, s2, v0 +; GCN-NEXT: ; return to shader part epilog + %val = call half @llvm.experimental.constrained.fmul.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret half %val +} + +define amdgpu_ps <2 x half> @s_constained_fmul_v2f16_fpexcept_strict(<2 x half> inreg %x, <2 x half> inreg %y) #0 { +; GFX9-LABEL: s_constained_fmul_v2f16_fpexcept_strict: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_pk_mul_f16 v0, s2, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: s_constained_fmul_v2f16_fpexcept_strict: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_lshr_b32 s0, s3, 16 +; GFX8-NEXT: s_lshr_b32 s1, s2, 16 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_mul_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_mul_f16_e32 v1, s2, v1 +; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: ; return to shader part epilog + %val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <2 x half> %val +} + +declare half @llvm.experimental.constrained.fmul.f16(half, half, metadata, metadata) #1 +declare <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half>, <2 x half>, metadata, metadata) #1 +declare <3 x half> @llvm.experimental.constrained.fmul.v3f16(<3 x half>, <3 x half>, metadata, metadata) #1 +declare <4 x half> @llvm.experimental.constrained.fmul.v4f16(<4 x half>, <4 x half>, metadata, metadata) #1 + +attributes #0 = { strictfp } +attributes #1 = { inaccessiblememonly nounwind willreturn } diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll new file mode 100644 index 0000000..a88391b --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll @@ -0,0 +1,129 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s + +define float @v_constained_fmul_f32_fpexcept_strict(float %x, float %y) #0 { +; GCN-LABEL: v_constained_fmul_f32_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call float @llvm.experimental.constrained.fmul.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret float %val +} + +define float @v_constained_fmul_f32_fpexcept_ignore(float %x, float %y) #0 { +; GCN-LABEL: v_constained_fmul_f32_fpexcept_ignore: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call float @llvm.experimental.constrained.fmul.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore") + ret float %val +} + +define float @v_constained_fmul_f32_fpexcept_maytrap(float %x, float %y) #0 { +; GCN-LABEL: v_constained_fmul_f32_fpexcept_maytrap: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call float @llvm.experimental.constrained.fmul.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap") + ret float %val +} + +define <2 x float> @v_constained_fmul_v2f32_fpexcept_strict(<2 x float> %x, <2 x float> %y) #0 { +; GCN-LABEL: v_constained_fmul_v2f32_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <2 x float> %val +} + +define <2 x float> @v_constained_fmul_v2f32_fpexcept_ignore(<2 x float> %x, <2 x float> %y) #0 { +; GCN-LABEL: v_constained_fmul_v2f32_fpexcept_ignore: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore") + ret <2 x float> %val +} + +define <2 x float> @v_constained_fmul_v2f32_fpexcept_maytrap(<2 x float> %x, <2 x float> %y) #0 { +; GCN-LABEL: v_constained_fmul_v2f32_fpexcept_maytrap: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap") + ret <2 x float> %val +} + +define <3 x float> @v_constained_fmul_v3f32_fpexcept_strict(<3 x float> %x, <3 x float> %y) #0 { +; GCN-LABEL: v_constained_fmul_v3f32_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, v0, v3 +; GCN-NEXT: v_mul_f32_e32 v1, v1, v4 +; GCN-NEXT: v_mul_f32_e32 v2, v2, v5 +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <3 x float> @llvm.experimental.constrained.fmul.v3f32(<3 x float> %x, <3 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <3 x float> %val +} + +define amdgpu_ps float @s_constained_fmul_f32_fpexcept_strict(float inreg %x, float inreg %y) #0 { +; GCN-LABEL: s_constained_fmul_f32_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, s3 +; GCN-NEXT: v_mul_f32_e32 v0, s2, v0 +; GCN-NEXT: ; return to shader part epilog + %val = call float @llvm.experimental.constrained.fmul.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret float %val +} + +define float @v_constained_fmul_f32_fpexcept_strict_fabs_lhs(float %x, float %y) #0 { +; GCN-LABEL: v_constained_fmul_f32_fpexcept_strict_fabs_lhs: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fabs.x = call float @llvm.fabs.f32(float %x) + %val = call float @llvm.experimental.constrained.fmul.f32(float %fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret float %val +} + +define float @v_constained_fmul_f32_fpexcept_strict_fabs_rhs(float %x, float %y) #0 { +; GCN-LABEL: v_constained_fmul_f32_fpexcept_strict_fabs_rhs: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e64 v0, v0, |v1| +; GCN-NEXT: s_setpc_b64 s[30:31] + %fabs.y = call float @llvm.fabs.f32(float %y) + %val = call float @llvm.experimental.constrained.fmul.f32(float %x, float %fabs.y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret float %val +} + +define float @v_constained_fmul_f32_fpexcept_strict_fneg_fabs_lhs(float %x, float %y) #0 { +; GCN-LABEL: v_constained_fmul_f32_fpexcept_strict_fneg_fabs_lhs: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fabs.x = call float @llvm.fabs.f32(float %x) + %neg.fabs.x = fneg float %fabs.x + %val = call float @llvm.experimental.constrained.fmul.f32(float %neg.fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret float %val +} + +declare float @llvm.fabs.f32(float) #1 +declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) #1 +declare <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float>, <2 x float>, metadata, metadata) #1 +declare <3 x float> @llvm.experimental.constrained.fmul.v3f32(<3 x float>, <3 x float>, metadata, metadata) #1 + +attributes #0 = { strictfp } +attributes #1 = { inaccessiblememonly nounwind willreturn } diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll new file mode 100644 index 0000000..0db8872 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll @@ -0,0 +1,96 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s + +define double @v_constained_fmul_f64_fpexcept_strict(double %x, double %y) #0 { +; GCN-LABEL: v_constained_fmul_f64_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call double @llvm.experimental.constrained.fmul.f64(double %x, double %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret double %val +} + +define double @v_constained_fmul_f64_fpexcept_ignore(double %x, double %y) #0 { +; GCN-LABEL: v_constained_fmul_f64_fpexcept_ignore: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call double @llvm.experimental.constrained.fmul.f64(double %x, double %y, metadata !"round.tonearest", metadata !"fpexcept.ignore") + ret double %val +} + +define double @v_constained_fmul_f64_fpexcept_maytrap(double %x, double %y) #0 { +; GCN-LABEL: v_constained_fmul_f64_fpexcept_maytrap: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call double @llvm.experimental.constrained.fmul.f64(double %x, double %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap") + ret double %val +} + +define <2 x double> @v_constained_fmul_v2f64_fpexcept_strict(<2 x double> %x, <2 x double> %y) #0 { +; GCN-LABEL: v_constained_fmul_v2f64_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GCN-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7] +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <2 x double> %val +} + +define <2 x double> @v_constained_fmul_v2f64_fpexcept_ignore(<2 x double> %x, <2 x double> %y) #0 { +; GCN-LABEL: v_constained_fmul_v2f64_fpexcept_ignore: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GCN-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7] +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore") + ret <2 x double> %val +} + +define <2 x double> @v_constained_fmul_v2f64_fpexcept_maytrap(<2 x double> %x, <2 x double> %y) #0 { +; GCN-LABEL: v_constained_fmul_v2f64_fpexcept_maytrap: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GCN-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7] +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap") + ret <2 x double> %val +} + +define <3 x double> @v_constained_fmul_v3f64_fpexcept_strict(<3 x double> %x, <3 x double> %y) #0 { +; GCN-LABEL: v_constained_fmul_v3f64_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7] +; GCN-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9] +; GCN-NEXT: v_mul_f64 v[4:5], v[4:5], v[10:11] +; GCN-NEXT: s_setpc_b64 s[30:31] + %val = call <3 x double> @llvm.experimental.constrained.fmul.v3f64(<3 x double> %x, <3 x double> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + ret <3 x double> %val +} + +define amdgpu_ps <2 x float> @s_constained_fmul_f64_fpexcept_strict(double inreg %x, double inreg %y) #0 { +; GCN-LABEL: s_constained_fmul_f64_fpexcept_strict: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: v_mul_f64 v[0:1], s[2:3], v[0:1] +; GCN-NEXT: ; return to shader part epilog + %val = call double @llvm.experimental.constrained.fmul.f64(double %x, double %y, metadata !"round.tonearest", metadata !"fpexcept.strict") + %cast = bitcast double %val to <2 x float> + ret <2 x float> %cast +} + +declare double @llvm.experimental.constrained.fmul.f64(double, double, metadata, metadata) #1 +declare <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double>, <2 x double>, metadata, metadata) #1 +declare <3 x double> @llvm.experimental.constrained.fmul.v3f64(<3 x double>, <3 x double>, metadata, metadata) #1 + +attributes #0 = { strictfp } +attributes #1 = { inaccessiblememonly nounwind willreturn } -- 2.7.4