From 648e422bd94312330be1ac1e7d8f988bcfefdc16 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 14 Jul 2016 05:23:23 +0000 Subject: [PATCH] AMDGPU/R600: Remove intrinsics with no tests and no users Mesa removed this path, so nothing is using these anymore. llvm-svn: 275372 --- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 8 ++++---- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 24 +--------------------- llvm/lib/Target/AMDGPU/R600Instructions.td | 30 +++------------------------- llvm/lib/Target/AMDGPU/R600Intrinsics.td | 29 +++++++-------------------- 4 files changed, 15 insertions(+), 76 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index d77f608..6761b4b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -12,7 +12,8 @@ // //===----------------------------------------------------------------------===// -class AMDGPUInst pattern> : Instruction { +class AMDGPUInst pattern = []> : Instruction { field bit isRegisterLoad = 0; field bit isRegisterStore = 0; @@ -35,11 +36,10 @@ class AMDGPUInst pattern> : Instructio let TSFlags{62} = isRegisterStore; } -class AMDGPUShaderInst pattern> - : AMDGPUInst { +class AMDGPUShaderInst pattern = []> : AMDGPUInst { field bits<32> Inst = 0xffffffff; - } def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">; diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 8651bd8..3ba4d4a0 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -669,24 +669,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const SDLoc DL(Op); switch(IntrinsicID) { default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); - case AMDGPUIntrinsic::R600_interp_xy: - case AMDGPUIntrinsic::R600_interp_zw: { - int slot = cast(Op.getOperand(1))->getZExtValue(); - MachineSDNode *interp; - SDValue RegisterINode = Op.getOperand(2); - SDValue RegisterJNode = Op.getOperand(3); - - if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy) - interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL, - MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), - RegisterJNode, RegisterINode); - else - interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL, - MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), - RegisterJNode, RegisterINode); - return DAG.getBuildVector(MVT::v2f32, DL, - {SDValue(interp, 0), SDValue(interp, 1)}); - } case AMDGPUIntrinsic::r600_tex: case AMDGPUIntrinsic::r600_texc: case AMDGPUIntrinsic::r600_txl: @@ -696,8 +678,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const case AMDGPUIntrinsic::r600_txf: case AMDGPUIntrinsic::r600_txq: case AMDGPUIntrinsic::r600_ddx: - case AMDGPUIntrinsic::r600_ddy: - case AMDGPUIntrinsic::R600_ldptr: { + case AMDGPUIntrinsic::r600_ddy: { unsigned TextureOp; switch (IntrinsicID) { case AMDGPUIntrinsic::r600_tex: @@ -730,9 +711,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const case AMDGPUIntrinsic::r600_ddy: TextureOp = 9; break; - case AMDGPUIntrinsic::R600_ldptr: - TextureOp = 10; - break; default: llvm_unreachable("Unknow Texture Operation"); } diff --git a/llvm/lib/Target/AMDGPU/R600Instructions.td b/llvm/lib/Target/AMDGPU/R600Instructions.td index 8414f99..13d8234 100644 --- a/llvm/lib/Target/AMDGPU/R600Instructions.td +++ b/llvm/lib/Target/AMDGPU/R600Instructions.td @@ -15,7 +15,7 @@ include "R600Intrinsics.td" include "R600InstrFormats.td" -class InstR600ISA pattern> : +class InstR600ISA pattern = []> : InstR600 { let Namespace = "AMDGPU"; @@ -434,8 +434,7 @@ def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, def INTERP_VEC_LOAD : AMDGPUShaderInst < (outs R600_Reg128:$dst), (ins i32imm:$src0), - "INTERP_LOAD $src0 : $dst", - [(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>; + "INTERP_LOAD $src0 : $dst">; def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { let bank_swizzle = 5; @@ -501,28 +500,6 @@ class ExportBufWord1 { } multiclass ExportPattern cf_inst> { - def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg), - (ExportInst - (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0), - 0, 61, 0, 7, 7, 7, cf_inst, 0) - >; - - def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg), - (ExportInst - (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0), - 0, 61, 7, 0, 7, 7, cf_inst, 0) - >; - - def : Pat<(int_R600_store_dummy (i32 imm:$type)), - (ExportInst - (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0) - >; - - def : Pat<(int_R600_store_dummy 1), - (ExportInst - (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0) - >; - def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), (ExportInst R600_Reg128:$src, imm:$type, imm:$base, @@ -1449,8 +1426,7 @@ def TEX_VTX_CONSTBUF : } def TEX_VTX_TEXBUF: - InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr", - [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>, + InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr">, VTX_WORD1_GPR, VTX_WORD0_eg { let VC_INST = 0; diff --git a/llvm/lib/Target/AMDGPU/R600Intrinsics.td b/llvm/lib/Target/AMDGPU/R600Intrinsics.td index 48e877f..68c4046 100644 --- a/llvm/lib/Target/AMDGPU/R600Intrinsics.td +++ b/llvm/lib/Target/AMDGPU/R600Intrinsics.td @@ -25,6 +25,13 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in { } let TargetPrefix = "R600", isTarget = 1 in { + def int_R600_store_swizzle : + Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_R600_store_stream_output : + Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; +} // End TargetPrefix = "R600", isTarget = 1 + +let TargetPrefix = "r600", isTarget = 1 in { class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [ llvm_v4f32_ty, // Coord @@ -52,29 +59,7 @@ let TargetPrefix = "R600", isTarget = 1 in { llvm_i32_ty // coord_type_w ], [IntrNoMem]>; - def int_R600_ldptr : TextureIntrinsicInt32Input; - def int_R600_interp_const : - Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>; - def int_R600_interp_xy : - Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; - def int_R600_interp_zw : - Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; - def int_R600_load_texbuf : - Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; - def int_R600_store_swizzle : - Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; - def int_R600_store_stream_output : - Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; - def int_R600_store_pixel_depth : - Intrinsic<[], [llvm_float_ty], []>; - def int_R600_store_pixel_stencil : - Intrinsic<[], [llvm_float_ty], []>; - def int_R600_store_dummy : - Intrinsic<[], [llvm_i32_ty], []>; -} // End TargetPrefix = "R600", isTarget = 1 - -let TargetPrefix = "r600", isTarget = 1 in { def int_r600_tex : TextureIntrinsicFloatInput; def int_r600_texc : TextureIntrinsicFloatInput; def int_r600_txl : TextureIntrinsicFloatInput; -- 2.7.4