From 646bd583daf8a4a585641479bd9a33d0822ff042 Mon Sep 17 00:00:00 2001 From: Zhuo Wang Date: Fri, 9 Feb 2018 19:18:10 +0800 Subject: [PATCH] dts: g12a: ethernet: re-organize ethernet dts/dtsi PD#156734: re-organize dts of ethernet Change-Id: I17724af9244fb1c2c06beceb8ef82f1550ddf8d6 Signed-off-by: Zhuo Wang --- arch/arm64/boot/dts/amlogic/g12a_skt.dts | 46 +++------------- arch/arm64/boot/dts/amlogic/mesong12a.dtsi | 15 ++++++ drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 65 ++++++++++++++--------- 3 files changed, 62 insertions(+), 64 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts index 9d95280..e2edb93 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts @@ -159,45 +159,6 @@ dev_name = "vout"; status = "okay"; }; -/*external_phy please use this - ethmac: ethernet@ff3f0000 { - compatible = "amlogic, g12a-eth-dwmac", "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000 - 0x0 0xff634540 0x0 0x8 - 0x0 0xff64c000 0x0 0xa0>; - reg-names = "eth_base", "eth_cfg", "eth_pll"; - interrupts = <0 8 1>; - interrupt-names = "macirq"; - status = "okay"; - clocks = <&clkc CLKID_ETH_CORE>; - clock-names = "ethclk81"; - - pinctrl-names = "external_eth_pins"; - pinctrl-0 = <&external_eth_pins>; - mc_val = <0x1621>; - - internal_phy=<0>; - }; - -*/ - ethmac: ethernet@ff3f0000 { - compatible = "amlogic, g12a-eth-dwmac","snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000 - 0x0 0xff634540 0x0 0x8 - 0x0 0xff64c000 0x0 0xa0>; - reg-names = "eth_base", "eth_cfg", "eth_pll"; - interrupts = <0 8 1>; - interrupt-names = "macirq"; - status = "okay"; - clocks = <&clkc CLKID_ETH_CORE>; - clock-names = "ethclk81"; - - pinctrl-names = "internal_eth_pins"; - pinctrl-0 = <&internal_eth_pins>; - mc_val = <0x4be04>; - - internal_phy=<1>; - }; amhdmitx: amhdmitx{ compatible = "amlogic, amhdmitx"; @@ -1625,4 +1586,11 @@ /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ controller-type = <3>; }; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + internal_phy=<1>; +}; diff --git a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi index f488a5f..733bc72 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi @@ -275,6 +275,21 @@ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ }; + ethmac: ethernet@ff3f0000 { + compatible = "amlogic, g12a-eth-dwmac","snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8 + 0x0 0xff64c000 0x0 0xa0>; + reg-names = "eth_base", "eth_cfg", "eth_pll"; + interrupts = <0 8 1>; + interrupt-names = "macirq"; + status = "disabled"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + }; + pinctrl_aobus: pinctrl@ff800014{ compatible = "amlogic,meson-g12a-aobus-pinctrl"; #address-cells = <2>; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c index 22fe60f..ed929a5 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c @@ -209,47 +209,62 @@ static void __iomem *network_interface_setup(struct platform_device *pdev) return PREG_ETH_REG0; } -static int dwmac_meson_cfg_pll(void __iomem *base_addr) +static int dwmac_meson_cfg_ctrl(void __iomem *base_addr) { void __iomem *ETH_PHY_config_addr = base_addr; - writel(0x19C0040A, ETH_PHY_config_addr + ETH_PLL_CTL0); - writel(0x927E0000, ETH_PHY_config_addr + ETH_PLL_CTL1); - writel(0x705B49e5, ETH_PHY_config_addr + ETH_PLL_CTL2); - writel(0x00000000, ETH_PHY_config_addr + ETH_PLL_CTL3); - usleep_range(100, 200); - writel(0x19C0040A, ETH_PHY_config_addr + ETH_PLL_CTL0); + /*config phyid should between a 0~0xffffffff*/ + /*please don't use 44000181, this has been used by internal phy*/ + writel(0x33000180, ETH_PHY_config_addr + ETH_PHY_CNTL0); + + /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/ + writel(0x260, ETH_PHY_config_addr + ETH_PHY_CNTL2); + + writel(0x74043, ETH_PHY_config_addr + ETH_PHY_CNTL1); + writel(0x34043, ETH_PHY_config_addr + ETH_PHY_CNTL1); + writel(0x74043, ETH_PHY_config_addr + ETH_PHY_CNTL1); return 0; } -static int dwmac_meson_cfg_analog(void __iomem *base_addr) +static int dwmac_meson_cfg_pll(void __iomem *base_addr, + struct platform_device *pdev) { void __iomem *ETH_PHY_config_addr = base_addr; + u32 pll_val[3] = {0}; - /*Analog*/ - writel(0x20200000, ETH_PHY_config_addr + ETH_PLL_CTL5); - writel(0x0000c002, ETH_PHY_config_addr + ETH_PLL_CTL6); - writel(0x00000023, ETH_PHY_config_addr + ETH_PLL_CTL7); + of_property_read_u32_array(pdev->dev.of_node, "pll_val", + pll_val, sizeof(pll_val) / sizeof(u32)); + pr_info("wzh pll %x %x %x", pll_val[0], pll_val[1], pll_val[2]); + writel(pll_val[0] | 0x30000000, ETH_PHY_config_addr + ETH_PLL_CTL0); + writel(pll_val[1], ETH_PHY_config_addr + ETH_PLL_CTL1); + writel(pll_val[2], ETH_PHY_config_addr + ETH_PLL_CTL2); + writel(0x00000000, ETH_PHY_config_addr + ETH_PLL_CTL3); + usleep_range(100, 200); + writel(pll_val[0] | 0x10000000, ETH_PHY_config_addr + ETH_PLL_CTL0); return 0; } -static int dwmac_meson_cfg_ctrl(void __iomem *base_addr) +static int dwmac_meson_cfg_analog(void __iomem *base_addr, + struct platform_device *pdev) { void __iomem *ETH_PHY_config_addr = base_addr; + u32 analog_val[3] = {0}; + + of_property_read_u32_array + (pdev->dev.of_node, "analog_val", + analog_val, + sizeof(analog_val) / sizeof(u32)); + pr_info("wzh analog %x %x %x", analog_val[0], + analog_val[1], analog_val[2]); + /*Analog*/ + writel(analog_val[0], ETH_PHY_config_addr + ETH_PLL_CTL5); + writel(analog_val[1], ETH_PHY_config_addr + ETH_PLL_CTL6); + writel(analog_val[2], ETH_PHY_config_addr + ETH_PLL_CTL7); - /*config phyid should between a 0~0xffffffff*/ - /*please don't use 44000181, this has been used by internal phy*/ - writel(0x33000180, ETH_PHY_config_addr + ETH_PHY_CNTL0); - - /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/ - writel(0x260, ETH_PHY_config_addr + ETH_PHY_CNTL2); - - writel(0x74043, ETH_PHY_config_addr + ETH_PHY_CNTL1); - writel(0x34043, ETH_PHY_config_addr + ETH_PHY_CNTL1); - writel(0x74043, ETH_PHY_config_addr + ETH_PHY_CNTL1); return 0; } + /*for newer then g12a use this dts architecture for dts*/ static void __iomem *g12a_network_interface_setup(struct platform_device *pdev) { @@ -310,8 +325,8 @@ static void __iomem *g12a_network_interface_setup(struct platform_device *pdev) /* Config G12A internal PHY */ if (internal_phy) { /*PLL*/ - dwmac_meson_cfg_pll(ETH_PHY_config_addr); - dwmac_meson_cfg_analog(ETH_PHY_config_addr); + dwmac_meson_cfg_pll(ETH_PHY_config_addr, pdev); + dwmac_meson_cfg_analog(ETH_PHY_config_addr, pdev); dwmac_meson_cfg_ctrl(ETH_PHY_config_addr); pin_ctl = devm_pinctrl_get_select (&pdev->dev, "internal_eth_pins"); -- 2.7.4