From 6469da2cb2148e7d46f65f69fcf7bbb979859dee Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Wed, 14 Aug 2013 20:38:33 +0000 Subject: [PATCH] re PR target/57949 ([powerpc64] Structure parameter alignment issue with vector extensions) gcc: 2013-08-14 Bill Schmidt PR target/57949 * doc/invoke.texi: Add documentation of mcompat-align-parm option. * config/rs6000/rs6000.opt: Add mcompat-align-parm option. * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX and Linux, correct BLKmode alignment when 128-bit alignment is required and compatibility flag is not set. (rs6000_gimplify_va_arg): For AIX and Linux, honor specified alignment for zero-size arguments when compatibility flag is not set. gcc/testsuite: 2013-08-14 Bill Schmidt PR target/57949 * gcc.target/powerpc/pr57949-1.c: New. * gcc.target/powerpc/pr57949-2.c: New. From-SVN: r201750 --- gcc/ChangeLog | 13 +++++++++++++ gcc/config/rs6000/rs6000.c | 9 +++++---- gcc/config/rs6000/rs6000.opt | 4 ++++ gcc/doc/invoke.texi | 19 ++++++++++++++++++- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/powerpc/pr57949-1.c | 19 +++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr57949-2.c | 19 +++++++++++++++++++ 7 files changed, 84 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr57949-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr57949-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c7f229b..1040af8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2013-08-14 Bill Schmidt + + PR target/57949 + * doc/invoke.texi: Add documentation of mcompat-align-parm + option. + * config/rs6000/rs6000.opt: Add mcompat-align-parm option. + * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX + and Linux, correct BLKmode alignment when 128-bit alignment is + required and compatibility flag is not set. + (rs6000_gimplify_va_arg): For AIX and Linux, honor specified + alignment for zero-size arguments when compatibility flag is not + set. + 2013-08-14 Jakub Jelinek PR tree-optimization/58145 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 30cd696..c1d4b99 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -8339,8 +8339,8 @@ rs6000_function_arg_boundary (enum machine_mode mode, const_tree type) || (type && TREE_CODE (type) == VECTOR_TYPE && int_size_in_bytes (type) >= 16)) return 128; - else if (TARGET_MACHO - && rs6000_darwin64_abi + else if (((TARGET_MACHO && rs6000_darwin64_abi) + || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) && mode == BLKmode && type && TYPE_ALIGN (type) > 64) return 128; @@ -9888,8 +9888,9 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, We don't need to check for pass-by-reference because of the test above. We can return a simplifed answer, since we know there's no offset to add. */ - if (TARGET_MACHO - && rs6000_darwin64_abi + if (((TARGET_MACHO + && rs6000_darwin64_abi) + || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) && integer_zerop (TYPE_SIZE (type))) { unsigned HOST_WIDE_INT align, boundary; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index f36e475..cd83cb2 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -546,3 +546,7 @@ Use ISA 2.07 transactional memory (HTM) instructions mquad-memory Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) Generate the quad word memory instructions (lq/stq/lqarx/stqcx). + +mcompat-align-parm +Target Report Var(rs6000_compat_align_parm) Init(0) Save +Generate aggregate parameter passing code with at most 64-bit alignment. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 66d7cc5..f6a4ec4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -871,7 +871,8 @@ See RS/6000 and PowerPC Options. -msave-toc-indirect -mno-save-toc-indirect @gol -mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol -mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol --mquad-memory -mno-quad-memory} +-mquad-memory -mno-quad-memory @gol +-mcompat-align-parm -mno-compat-align-parm} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -18417,6 +18418,22 @@ stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The @option{-mno-save-toc-indirect} option is the default. + +@item -mcompat-align-parm +@itemx -mno-compat-align-parm +@opindex mcompat-align-parm +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of GCC. + +Older versions of GCC (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128-bit boundary when that structure contained +a member requiring 128-bit alignment. This is corrected in more +recent versions of GCC. This option may be used to generate code +that is compatible with functions compiled with older versions of +GCC. + +The @option{-mno-compat-align-parm} option is the default. @end table @node RX Options diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c56c260..72fcd60 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2013-08-14 Bill Schmidt + + PR target/57949 + * gcc.target/powerpc/pr57949-1.c: New. + * gcc.target/powerpc/pr57949-2.c: New. + 2013-08-14 Jakub Jelinek PR tree-optimization/58145 diff --git a/gcc/testsuite/gcc.target/powerpc/pr57949-1.c b/gcc/testsuite/gcc.target/powerpc/pr57949-1.c new file mode 100644 index 0000000..253b2d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr57949-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ + +/* Verify that vs is 16-byte aligned in the absence of -mcompat-align-parm. */ + +typedef float v4sf __attribute__ ((vector_size (16))); +struct s { long m; v4sf v; }; +long n; +v4sf ve; + +void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6, + long d7, long d8, long d9, struct s vs) { + n = vs.m; + ve = vs.v; +} + +/* { dg-final { scan-assembler "li \.\*,144" } } */ +/* { dg-final { scan-assembler "ld \.\*,128\\(1\\)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr57949-2.c b/gcc/testsuite/gcc.target/powerpc/pr57949-2.c new file mode 100644 index 0000000..aa6a0d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr57949-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7 -mcompat-align-parm" } */ + +/* Verify that vs is not 16-byte aligned with -mcompat-align-parm. */ + +typedef float v4sf __attribute__ ((vector_size (16))); +struct s { long m; v4sf v; }; +long n; +v4sf ve; + +void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6, + long d7, long d8, long d9, struct s vs) { + n = vs.m; + ve = vs.v; +} + +/* { dg-final { scan-assembler "ld .\*,136\\(1\\)" } } */ +/* { dg-final { scan-assembler "ld .\*,120\\(1\\)" } } */ -- 2.7.4