From 645bfe04ce118a462ad2b3d59a323619dea95560 Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Tue, 14 Feb 2023 21:46:12 +0800 Subject: [PATCH] RISC-V: Add vwmacc vv C api tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwmacc_vv-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwmacc_vv-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c | 111 +++++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c | 111 +++++++++++++++++++++ 54 files changed, 5994 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c new file mode 100644 index 0000000..803dfa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c new file mode 100644 index 0000000..88a0a12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c new file mode 100644 index 0000000..33f733c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c new file mode 100644 index 0000000..0d6390c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_m(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_m(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_m(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_m(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_m(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_m(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_m(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_m(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_m(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_m(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_m(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_m(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_m(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_m(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_m(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c new file mode 100644 index 0000000..df359bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_m(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_m(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_m(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_m(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_m(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_m(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_m(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_m(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_m(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_m(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_m(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_m(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_m(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_m(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_m(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c new file mode 100644 index 0000000..c1408b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_m(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_m(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_m(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_m(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_m(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_m(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_m(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_m(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_m(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_m(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_m(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_m(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_m(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_m(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_m(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c new file mode 100644 index 0000000..5032a08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_mu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_mu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_mu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c new file mode 100644 index 0000000..731e267 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_mu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_mu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_mu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_mu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_mu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_mu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_mu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_mu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_mu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_mu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_mu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_mu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_mu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_mu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_mu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c new file mode 100644 index 0000000..c4643ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_mu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_mu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_mu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_mu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_mu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_mu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_mu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_mu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_mu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_mu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_mu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_mu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_mu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_mu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_mu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c new file mode 100644 index 0000000..1147582 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tu(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tu(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tu(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tu(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tu(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tu(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tu(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tu(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tu(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tu(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tu(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tu(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tu(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tu(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tu(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c new file mode 100644 index 0000000..3d21a06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tu(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tu(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tu(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tu(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tu(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tu(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tu(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tu(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tu(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tu(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tu(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tu(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tu(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tu(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tu(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c new file mode 100644 index 0000000..4c258c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tu(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tu(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tu(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tu(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tu(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tu(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tu(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tu(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tu(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tu(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tu(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tu(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tu(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tu(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tu(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c new file mode 100644 index 0000000..c65c026 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tum(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tum(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tum(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c new file mode 100644 index 0000000..513b6c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tum(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tum(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tum(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tum(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tum(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tum(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tum(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tum(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tum(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tum(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tum(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tum(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tum(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tum(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tum(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c new file mode 100644 index 0000000..a1ce9b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tum(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tum(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tum(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tum(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tum(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tum(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tum(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tum(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tum(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tum(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tum(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tum(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tum(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tum(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tum(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c new file mode 100644 index 0000000..751da6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tumu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c new file mode 100644 index 0000000..e78de68 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tumu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tumu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tumu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c new file mode 100644 index 0000000..51c6d32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf4_tumu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16mf2_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m1_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m2_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m4_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i16m8_tumu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32mf2_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m1_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m2_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m4_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i32m8_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m1_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m2_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m4_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_vv_i64m8_tumu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c new file mode 100644 index 0000000..b69b9d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c new file mode 100644 index 0000000..65e728f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c new file mode 100644 index 0000000..918c5fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c new file mode 100644 index 0000000..56c482e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_m(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_m(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_m(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_m(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_m(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_m(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_m(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_m(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_m(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_m(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_m(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_m(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_m(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_m(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_m(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c new file mode 100644 index 0000000..a8c4250 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_m(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_m(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_m(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_m(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_m(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_m(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_m(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_m(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_m(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_m(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_m(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_m(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_m(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_m(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_m(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c new file mode 100644 index 0000000..a2284ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_m(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_m(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_m(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_m(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_m(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_m(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_m(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_m(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_m(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_m(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_m(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_m(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_m(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_m(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_m(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c new file mode 100644 index 0000000..a2e7cd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_mu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_mu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_mu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c new file mode 100644 index 0000000..fe32bfb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_mu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_mu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_mu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_mu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_mu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_mu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_mu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_mu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_mu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_mu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_mu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_mu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_mu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_mu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_mu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c new file mode 100644 index 0000000..3e33291 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_mu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_mu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_mu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_mu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_mu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_mu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_mu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_mu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_mu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_mu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_mu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_mu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_mu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_mu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_mu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c new file mode 100644 index 0000000..a32ffc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tu(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tu(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tu(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tu(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tu(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tu(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tu(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tu(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tu(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tu(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tu(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tu(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tu(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tu(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tu(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c new file mode 100644 index 0000000..82c390ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tu(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tu(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tu(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tu(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tu(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tu(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tu(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tu(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tu(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tu(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tu(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tu(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tu(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tu(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tu(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c new file mode 100644 index 0000000..5fe0236 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tu(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tu(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tu(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tu(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tu(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tu(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tu(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tu(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tu(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tu(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tu(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tu(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tu(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tu(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tu(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c new file mode 100644 index 0000000..a75b8e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tum(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tum(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tum(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c new file mode 100644 index 0000000..4c4cd28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tum(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tum(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tum(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tum(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tum(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tum(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tum(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tum(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tum(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tum(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tum(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tum(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tum(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tum(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tum(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c new file mode 100644 index 0000000..f255481 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tum(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tum(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tum(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tum(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tum(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tum(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tum(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tum(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tum(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tum(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tum(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tum(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tum(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tum(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tum(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c new file mode 100644 index 0000000..58f492b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tumu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c new file mode 100644 index 0000000..df7b038 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tumu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tumu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tumu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c new file mode 100644 index 0000000..31bba28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf4_tumu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16mf2_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m1_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m2_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m4_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i16m8_tumu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32mf2_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m1_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m2_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m4_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i32m8_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m1_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m2_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m4_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_vv_i64m8_tumu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c new file mode 100644 index 0000000..35662bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4(vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2(vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1(vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2(vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4(vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8(vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2(vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1(vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2(vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4(vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8(vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1(vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2(vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4(vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c new file mode 100644 index 0000000..5b00b68 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4(vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2(vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1(vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2(vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4(vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8(vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2(vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1(vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2(vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4(vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8(vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1(vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2(vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4(vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c new file mode 100644 index 0000000..c0f57af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4(vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2(vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1(vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2(vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4(vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8(vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2(vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1(vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2(vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4(vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8(vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1(vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2(vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4(vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c new file mode 100644 index 0000000..596aa21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_m(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_m(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_m(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_m(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_m(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_m(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_m(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_m(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_m(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_m(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_m(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_m(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_m(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_m(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_m(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_m(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_m(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_m(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_m(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_m(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_m(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_m(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_m(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_m(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_m(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_m(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_m(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c new file mode 100644 index 0000000..d855092 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_m(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_m(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_m(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_m(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_m(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_m(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_m(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_m(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_m(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_m(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_m(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_m(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_m(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_m(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_m(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_m(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_m(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_m(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_m(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_m(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_m(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_m(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_m(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_m(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_m(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_m(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_m(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c new file mode 100644 index 0000000..a942bc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_m(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_m(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_m(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_m(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_m(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_m(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_m(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_m(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_m(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_m(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_m(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_m(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_m(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_m(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_m(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_m(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_m(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_m(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_m(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_m(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_m(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_m(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_m(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_m(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_m(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_m(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_m(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c new file mode 100644 index 0000000..4626f95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_mu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c new file mode 100644 index 0000000..6ee2a1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_mu(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_mu(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_mu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c new file mode 100644 index 0000000..2496bb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_mu(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_mu(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_mu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c new file mode 100644 index 0000000..db9ab35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tu(vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tu(vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tu(vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tu(vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tu(vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tu(vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tu(vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tu(vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tu(vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tu(vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tu(vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tu(vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tu(vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tu(vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tu(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c new file mode 100644 index 0000000..6604dc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tu(vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tu(vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tu(vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tu(vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tu(vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tu(vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tu(vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tu(vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tu(vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tu(vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tu(vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tu(vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tu(vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tu(vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tu(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c new file mode 100644 index 0000000..6dcccbc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tu(vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tu(vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tu(vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tu(vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tu(vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tu(vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tu(vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tu(vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tu(vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tu(vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tu(vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tu(vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tu(vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tu(vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tu(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c new file mode 100644 index 0000000..1683f8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tum(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c new file mode 100644 index 0000000..4d2fd2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tum(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tum(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tum(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c new file mode 100644 index 0000000..36972c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tum(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tum(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tum(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c new file mode 100644 index 0000000..4d74c75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tumu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c new file mode 100644 index 0000000..42a56c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tumu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c new file mode 100644 index 0000000..88c48ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf4_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16mf2_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m1_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m2_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m4_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u16m8_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32mf2_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m1_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m2_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m4_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u32m8_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m1_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m2_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m4_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_vv_u64m8_tumu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -- 2.7.4