From 6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d Mon Sep 17 00:00:00 2001 From: Stephen Hines Date: Fri, 11 Jun 2021 02:07:59 -0700 Subject: [PATCH] [compiler-rt] [builtins] [AArch64] Add missing AArch64 data synchronization barrier (dsb) to __clear_cache https://developer.arm.com/documentation/den0024/a/Caches/Cache-maintenance covers how to properly clear caches on AArch64, and the builtin implementation was missing a `dsb ish` after clearing the icache for the selected range. Reviewed By: kristof.beyls Differential Revision: https://reviews.llvm.org/D104094 --- compiler-rt/lib/builtins/clear_cache.c | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c index 5a443dd..0284cb6 100644 --- a/compiler-rt/lib/builtins/clear_cache.c +++ b/compiler-rt/lib/builtins/clear_cache.c @@ -126,6 +126,7 @@ void __clear_cache(void *start, void *end) { addr += icache_line_size) __asm __volatile("ic ivau, %0" ::"r"(addr)); } + __asm __volatile("dsb ish"); __asm __volatile("isb sy"); #elif defined(__powerpc64__) const size_t line_size = 32; -- 2.7.4