From 643792048ee84b199052e9c8f89253649ca78922 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Tue, 20 Sep 2022 09:00:18 -0700 Subject: [PATCH] serial: sifive: enable clocks for UART when probed MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit When the PWM driver was changed to disable clocks if no PWMs are enabled, it ended up also disabling the shared parent with the UART, since the UART doesn't do any clock enablement on its own. To avoid these surprises, switch to clk_get_enabled(). Fixes: ace41d7564e655 ("pwm: sifive: Ensure the clk is enabled exactly once per running PWM") Cc: stable Cc: Uwe Kleine-König Cc: Emil Renner Berthing Cc: Palmer Dabbelt Cc: Paul Walmsley Reviewed-by: Palmer Dabbelt Reviewed-by: Uwe Kleine-König Acked-by: Palmer Dabbelt Signed-off-by: Olof Johansson Link: https://lore.kernel.org/r/20220920160017.7315-1-olof@lixom.net Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/sifive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c index 5c3a07546a58..4b1d4fe8458e 100644 --- a/drivers/tty/serial/sifive.c +++ b/drivers/tty/serial/sifive.c @@ -945,7 +945,7 @@ static int sifive_serial_probe(struct platform_device *pdev) return PTR_ERR(base); } - clk = devm_clk_get(&pdev->dev, NULL); + clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(clk)) { dev_err(&pdev->dev, "unable to find controller clock\n"); return PTR_ERR(clk); -- 2.34.1