From 63aff5cd3c83cc1000cf9c85388e62071086dda2 Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 2 Dec 2019 14:46:22 +0000 Subject: [PATCH] [ARM] More reversed vcmp tests. NFC --- llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll | 2611 ++++++++++++++++++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll | 2493 ++++++++++++++++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-vcmpr.ll | 593 ++++++++ llvm/test/CodeGen/Thumb2/mve-vcmpz.ll | 418 +++++ 4 files changed, 6115 insertions(+) diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll index 22483aa..79700e0 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll @@ -2609,3 +2609,2614 @@ entry: %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b ret <8 x half> %s } + + +; Reversed + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp oeq <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_one_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r3, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp one <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp ogt <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_oge_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp oge <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_olt_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp olt <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ole_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp ole <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r3, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp ueq <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_une_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp une <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp ugt <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_uge_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp uge <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ult_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp ult <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ule_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp ule <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ord_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp ord <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_uno_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s4, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s2 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s4, s3 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov r0, s4 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 +; CHECK-MVEFP-NEXT: bx lr +entry: + %i = insertelement <4 x float> undef, float %src2, i32 0 + %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer + %c = fcmp uno <4 x float> %sp, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + + + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp oeq <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_one_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp one <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp ogt <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp oge <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp olt <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp ole <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp ueq <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_une_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp une <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp ugt <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp uge <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp ult <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp ule <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp ord <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half* %src2p, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9, d10} +; CHECK-MVE-NEXT: vpush {d8, d9, d10} +; CHECK-MVE-NEXT: vldr.16 s16, [r0] +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: vcmp.f16 s16, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: movs r2, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s20, s9 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r0, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[2], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s5 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s2 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s20, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vmovx.f16 s18, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s18 +; CHECK-MVE-NEXT: vmov.16 q3[4], r0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s18, s6 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vcmp.f16 s16, s3 +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: vcmp.f16 s16, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: vmov r0, s18 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov.16 q3[6], r0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9, d10} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vldr.16 s12, [r0] +; CHECK-MVEFP-NEXT: vmov r0, s12 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 +; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %src2 = load half, half* %src2p + %i = insertelement <8 x half> undef, half %src2, i32 0 + %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer + %c = fcmp uno <8 x half> %sp, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll index 6aae7e7..b9e7ad6 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll @@ -2491,3 +2491,2496 @@ entry: %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b ret <8 x half> %s } + + +; Reversed + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp oeq <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_one_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r3, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f32 le, q3, q0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp one <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ogt <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_oge_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp oge <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_olt_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp olt <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ole_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ole <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r3, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f32 le, q3, q0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ueq <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_une_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp une <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ugt <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_uge_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp uge <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ult_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ult <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ule_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ule <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_ord_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, s2 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, s3 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q3, q0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ord <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + +define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { +; CHECK-MVE-LABEL: vcmp_r_uno_v4f32: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: vcmp.f32 s0, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, s1 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, s2 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, s3 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r3, #1 +; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: cset r3, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 +; CHECK-MVE-NEXT: lsls r0, r3, #31 +; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 +; CHECK-MVE-NEXT: lsls r0, r2, #31 +; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 +; CHECK-MVE-NEXT: lsls r0, r1, #31 +; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f32 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q3, q0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp uno <4 x float> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %s +} + + + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp oeq <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_one_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f16 le, q3, q0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp one <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it mi +; CHECK-MVE-NEXT: movmi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ogt <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ls +; CHECK-MVE-NEXT: movls r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp oge <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it gt +; CHECK-MVE-NEXT: movgt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp olt <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ge +; CHECK-MVE-NEXT: movge r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ole <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r2, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: mov.w r0, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r1, #1 +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it eq +; CHECK-MVE-NEXT: moveq r0, #1 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f16 le, q3, q0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ueq <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_une_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it ne +; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp une <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it lt +; CHECK-MVE-NEXT: movlt r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ugt <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it le +; CHECK-MVE-NEXT: movle r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp uge <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it hi +; CHECK-MVE-NEXT: movhi r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ult <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, #0 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, #0 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, #0 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, #0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it pl +; CHECK-MVE-NEXT: movpl r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ule <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, s0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s16 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, s2 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s16 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, s3 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vc +; CHECK-MVE-NEXT: movvc r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q3, q0 +; CHECK-MVEFP-NEXT: vpnot +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp ord <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} + +define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { +; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: +; CHECK-MVE: @ %bb.0: @ %entry +; CHECK-MVE-NEXT: .vsave {d8, d9} +; CHECK-MVE-NEXT: vpush {d8, d9} +; CHECK-MVE-NEXT: vmovx.f16 s12, s0 +; CHECK-MVE-NEXT: movs r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s12, s12 +; CHECK-MVE-NEXT: vmovx.f16 s12, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vcmp.f16 s0, s0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s14, s8 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: mov.w r2, #0 +; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r2, #1 +; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: cset r2, ne +; CHECK-MVE-NEXT: vmov r1, s12 +; CHECK-MVE-NEXT: lsls r2, r2, #31 +; CHECK-MVE-NEXT: vcmp.f16 s1, s1 +; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r2, s12 +; CHECK-MVE-NEXT: vmovx.f16 s18, s9 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmovx.f16 s0, s3 +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: movs r0, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s1 +; CHECK-MVE-NEXT: vcmp.f16 s16, s16 +; CHECK-MVE-NEXT: vmov.16 q3[2], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s5 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s2, s2 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s18, s10 +; CHECK-MVE-NEXT: vmov.16 q3[3], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vmovx.f16 s16, s2 +; CHECK-MVE-NEXT: vcmp.f16 s16, s16 +; CHECK-MVE-NEXT: vmov.16 q3[4], r1 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s16, s6 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vcmp.f16 s3, s3 +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: vcmp.f16 s0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[5], r1 +; CHECK-MVE-NEXT: mov.w r1, #0 +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r1, #1 +; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: cset r1, ne +; CHECK-MVE-NEXT: vmovx.f16 s0, s7 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmovx.f16 s2, s11 +; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr +; CHECK-MVE-NEXT: it vs +; CHECK-MVE-NEXT: movvs r0, #1 +; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: cset r0, ne +; CHECK-MVE-NEXT: vmov r1, s16 +; CHECK-MVE-NEXT: lsls r0, r0, #31 +; CHECK-MVE-NEXT: vmov.16 q3[6], r1 +; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 +; CHECK-MVE-NEXT: vmov r0, s0 +; CHECK-MVE-NEXT: vmov.16 q3[7], r0 +; CHECK-MVE-NEXT: vmov q0, q3 +; CHECK-MVE-NEXT: vpop {d8, d9} +; CHECK-MVE-NEXT: bx lr +; +; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: +; CHECK-MVEFP: @ %bb.0: @ %entry +; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0 +; CHECK-MVEFP-NEXT: vpt.f16 le, q0, q3 +; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q3, q0 +; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 +; CHECK-MVEFP-NEXT: bx lr +entry: + %c = fcmp uno <8 x half> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b + ret <8 x half> %s +} diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll index a6fc2db..c832c24 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll @@ -591,3 +591,596 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, < %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 ret <2 x i32> %a11 } + +; Reversed + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_eq_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i32 eq, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp eq <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ne_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ne_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i32 ne, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp ne <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_sgt_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 lt, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp sgt <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_sge_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 le, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp sge <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_slt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_slt_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 gt, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp slt <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sle_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_sle_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 ge, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp sle <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ugt_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vdup.32 q3, r0 +; CHECK-NEXT: vcmp.u32 hi, q3, q0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp ugt <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_uge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_uge_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vdup.32 q3, r0 +; CHECK-NEXT: vcmp.u32 cs, q3, q0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp uge <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ult_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ult_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u32 hi, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp ult <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ule_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ule_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u32 cs, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <4 x i32> undef, i32 %src2, i32 0 + %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer + %c = icmp ule <4 x i32> %sp, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_eq_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_eq_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i16 eq, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp eq <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ne_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ne_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i16 ne, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp ne <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_sgt_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 lt, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp sgt <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_sge_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 le, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp sge <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_slt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_slt_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 gt, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp slt <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sle_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_sle_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 ge, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp sle <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ugt_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vdup.16 q3, r0 +; CHECK-NEXT: vcmp.u16 hi, q3, q0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp ugt <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_uge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_uge_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vdup.16 q3, r0 +; CHECK-NEXT: vcmp.u16 cs, q3, q0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp uge <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ult_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ult_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u16 hi, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp ult <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ule_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ule_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u16 cs, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <8 x i16> undef, i16 %src2, i32 0 + %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer + %c = icmp ule <8 x i16> %sp, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_eq_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_eq_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i8 eq, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp eq <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ne_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ne_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i8 ne, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp ne <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_sgt_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 lt, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp sgt <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_sge_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 le, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp sge <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_slt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_slt_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 gt, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp slt <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sle_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_sle_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 ge, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp sle <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ugt_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vdup.8 q3, r0 +; CHECK-NEXT: vcmp.u8 hi, q3, q0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp ugt <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_uge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_uge_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vdup.8 q3, r0 +; CHECK-NEXT: vcmp.u8 cs, q3, q0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp uge <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ult_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ult_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u8 hi, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp ult <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ule_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ule_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u8 cs, q0, r0 +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <16 x i8> undef, i8 %src2, i32 0 + %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer + %c = icmp ule <16 x i8> %sp, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + + +define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: vcmp_r_eq_v2i64: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov r2, s1 +; CHECK-NEXT: vmov r3, s0 +; CHECK-NEXT: eors r2, r1 +; CHECK-NEXT: eors r3, r0 +; CHECK-NEXT: orrs r2, r3 +; CHECK-NEXT: cset r2, eq +; CHECK-NEXT: tst.w r2, #1 +; CHECK-NEXT: csetm r2, ne +; CHECK-NEXT: vmov.32 q3[0], r2 +; CHECK-NEXT: vmov.32 q3[1], r2 +; CHECK-NEXT: vmov r2, s3 +; CHECK-NEXT: eors r1, r2 +; CHECK-NEXT: vmov r2, s2 +; CHECK-NEXT: eors r0, r2 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vbic q0, q2, q3 +; CHECK-NEXT: vand q1, q1, q3 +; CHECK-NEXT: vorr q0, q1, q0 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <2 x i64> undef, i64 %src2, i32 0 + %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer + %c = icmp eq <2 x i64> %sp, %src + %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b + ret <2 x i64> %s +} + +define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) { +; CHECK-LABEL: vcmp_r_eq_v2i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov r2, s1 +; CHECK-NEXT: vmov r3, s0 +; CHECK-NEXT: eors r2, r1 +; CHECK-NEXT: eors r3, r0 +; CHECK-NEXT: orrs r2, r3 +; CHECK-NEXT: cset r2, eq +; CHECK-NEXT: tst.w r2, #1 +; CHECK-NEXT: csetm r2, ne +; CHECK-NEXT: vmov.32 q3[0], r2 +; CHECK-NEXT: vmov.32 q3[1], r2 +; CHECK-NEXT: vmov r2, s3 +; CHECK-NEXT: eors r1, r2 +; CHECK-NEXT: vmov r2, s2 +; CHECK-NEXT: eors r0, r2 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vbic q0, q2, q3 +; CHECK-NEXT: vand q1, q1, q3 +; CHECK-NEXT: vorr q0, q1, q0 +; CHECK-NEXT: bx lr +entry: + %i = insertelement <2 x i64> undef, i64 %src2, i32 0 + %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer + %c = icmp eq <2 x i64> %sp, %src + %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b + ret <2 x i32> %s +} + +define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) { +; CHECK-LABEL: vcmp_r_multi_v2i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: .vsave {d8, d9, d10, d11} +; CHECK-NEXT: vpush {d8, d9, d10, d11} +; CHECK-NEXT: vmov r0, s1 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: vmov r1, s0 +; CHECK-NEXT: vmov r2, s8 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov r0, s3 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vbic q0, q2, q3 +; CHECK-NEXT: vmov lr, s0 +; CHECK-NEXT: subs.w r1, lr, r2 +; CHECK-NEXT: asr.w r12, lr, #31 +; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: vmov r2, s10 +; CHECK-NEXT: it lt +; CHECK-NEXT: movlt r1, #1 +; CHECK-NEXT: cmp r1, #0 +; CHECK-NEXT: csetm r1, ne +; CHECK-NEXT: vmov.32 q3[0], r1 +; CHECK-NEXT: vmov.32 q3[1], r1 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: subs r0, r1, r2 +; CHECK-NEXT: asr.w r12, r1, #31 +; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31 +; CHECK-NEXT: it lt +; CHECK-NEXT: movlt r3, #1 +; CHECK-NEXT: cmp r3, #0 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: cmp.w lr, #0 +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: cset r0, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: cmp r1, #0 +; CHECK-NEXT: vmov.32 q4[0], r0 +; CHECK-NEXT: vmov.32 q4[1], r0 +; CHECK-NEXT: cset r0, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q4[2], r0 +; CHECK-NEXT: vmov.32 q4[3], r0 +; CHECK-NEXT: vmov r0, s4 +; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: cset r0, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q5[0], r0 +; CHECK-NEXT: vmov.32 q5[1], r0 +; CHECK-NEXT: vmov r0, s6 +; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: cset r0, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q5[2], r0 +; CHECK-NEXT: vmov.32 q5[3], r0 +; CHECK-NEXT: vand q1, q5, q4 +; CHECK-NEXT: vand q1, q3, q1 +; CHECK-NEXT: vbic q0, q0, q1 +; CHECK-NEXT: vand q1, q2, q1 +; CHECK-NEXT: vorr q0, q1, q0 +; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: pop {r7, pc} + %a4 = icmp eq <2 x i64> %a, zeroinitializer + %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c + %a6 = icmp ne <2 x i32> %b, zeroinitializer + %a7 = icmp slt <2 x i32> %a5, %c + %a8 = icmp ne <2 x i32> %a5, zeroinitializer + %a9 = and <2 x i1> %a6, %a8 + %a10 = and <2 x i1> %a7, %a9 + %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 + ret <2 x i32> %a11 +} diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll index 142511b..6d08abc 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll @@ -415,3 +415,421 @@ entry: %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b ret <2 x i32> %s } + + +; Reversed + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_eqz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_eqz_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i32 eq, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_nez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_nez_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i32 ne, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ne <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_sgtz_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 lt, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sgt <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_sgez_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 le, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sge <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sltz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_sltz_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 gt, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp slt <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_slez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_slez_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s32 ge, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sle <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ugtz_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ugt <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ugez_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u32 cs, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp uge <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ultz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ultz_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i32 ne, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ult <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + +define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ulez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: vcmp_r_ulez_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp ule <4 x i32> zeroinitializer, %src + %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %s +} + + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_eqz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_eqz_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i16 eq, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_nez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_nez_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i16 ne, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ne <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_sgtz_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 lt, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sgt <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_sgez_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 le, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sge <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sltz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_sltz_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 gt, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp slt <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_slez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_slez_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s16 ge, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sle <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ugtz_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ugt <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ugez_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u16 cs, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp uge <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ultz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ultz_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i16 ne, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ult <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + +define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ulez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: vcmp_r_ulez_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp ule <8 x i16> zeroinitializer, %src + %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %s +} + + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_eqz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_eqz_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i8 eq, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_nez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_nez_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i8 ne, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ne <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_sgtz_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 lt, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sgt <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_sgez_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 le, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sge <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sltz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_sltz_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 gt, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp slt <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_slez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_slez_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.s8 ge, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp sle <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ugtz_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ugt <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ugez_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.u8 cs, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp uge <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ultz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ultz_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcmp.i8 ne, q0, zr +; CHECK-NEXT: vpsel q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %c = icmp ult <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + +define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ulez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: vcmp_r_ulez_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp ule <16 x i8> zeroinitializer, %src + %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %s +} + + +define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: vcmp_r_eqz_v2i64: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov r0, s1 +; CHECK-NEXT: vmov r1, s0 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov r0, s3 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vbic q0, q2, q3 +; CHECK-NEXT: vand q1, q1, q3 +; CHECK-NEXT: vorr q0, q1, q0 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <2 x i64> zeroinitializer, %src + %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b + ret <2 x i64> %s +} + +define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <2 x i32> %b) { +; CHECK-LABEL: vcmp_r_eqz_v2i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov r0, s1 +; CHECK-NEXT: vmov r1, s0 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov r0, s3 +; CHECK-NEXT: orrs r0, r1 +; CHECK-NEXT: cset r0, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vbic q0, q2, q3 +; CHECK-NEXT: vand q1, q1, q3 +; CHECK-NEXT: vorr q0, q1, q0 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <2 x i64> %src, zeroinitializer + %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b + ret <2 x i32> %s +} -- 2.7.4