From 6391f9ab4cb2b6cb26b559bc33a8e8851af65745 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 4 Jun 2020 10:39:51 +0200 Subject: [PATCH] aco: fix nir_intrinsic_quad_* with 8-bit in GFX6-GFX7 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index fed67bf..ccfb17e 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -7761,7 +7761,10 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) emit_wqm(ctx, tmp, dst); } else if (instr->dest.ssa.bit_size == 8) { Temp tmp = bld.tmp(v1); - emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + if (ctx->program->chip_class >= GFX8) + emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + else + emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), tmp); bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v3b), tmp); } else if (instr->dest.ssa.bit_size == 16) { Temp tmp = bld.tmp(v1); @@ -7836,7 +7839,10 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) emit_wqm(ctx, tmp, dst); } else if (instr->dest.ssa.bit_size == 8) { Temp tmp = bld.tmp(v1); - emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + if (ctx->program->chip_class >= GFX8) + emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + else + emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl), tmp); bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v3b), tmp); } else if (instr->dest.ssa.bit_size == 16) { Temp tmp = bld.tmp(v1); -- 2.7.4