From 63774642af1efb127c6e3eafdd44eadc54647141 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 3 Jul 2020 11:52:52 -0400 Subject: [PATCH] [InstCombine] add one-use check to cast+select narrowing transform Prevent increasing the instruction count. --- llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | 2 +- llvm/test/Transforms/InstCombine/select-bitext.ll | 6 ++---- llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll | 3 +-- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index cef991a..8200310 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -1930,7 +1930,7 @@ Instruction *InstCombiner::foldSelectExtConst(SelectInst &Sel) { Type *SelType = Sel.getType(); Constant *TruncC = ConstantExpr::getTrunc(C, SmallType); Constant *ExtC = ConstantExpr::getCast(ExtOpcode, TruncC, SelType); - if (ExtC == C) { + if (ExtC == C && ExtInst->hasOneUse()) { Value *TruncCVal = cast(TruncC); if (ExtInst == Sel.getFalseValue()) std::swap(X, TruncCVal); diff --git a/llvm/test/Transforms/InstCombine/select-bitext.ll b/llvm/test/Transforms/InstCombine/select-bitext.ll index d39dca9..1e156e2 100644 --- a/llvm/test/Transforms/InstCombine/select-bitext.ll +++ b/llvm/test/Transforms/InstCombine/select-bitext.ll @@ -458,8 +458,7 @@ define i32 @sel_sext_const_uses(i8 %a, i8 %x) { ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i8 [[X:%.*]], 15 ; CHECK-NEXT: [[A_EXT:%.*]] = sext i8 [[A:%.*]] to i32 ; CHECK-NEXT: call void @use32(i32 [[A_EXT]]) -; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[COND]], i8 [[A]], i8 127 -; CHECK-NEXT: [[R:%.*]] = sext i8 [[NARROW]] to i32 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND]], i32 [[A_EXT]], i32 127 ; CHECK-NEXT: ret i32 [[R]] ; %cond = icmp ugt i8 %x, 15 @@ -474,8 +473,7 @@ define i32 @sel_zext_const_uses(i8 %a, i8 %x) { ; CHECK-NEXT: [[COND:%.*]] = icmp sgt i8 [[X:%.*]], 15 ; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 [[A:%.*]] to i32 ; CHECK-NEXT: call void @use32(i32 [[A_EXT]]) -; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[COND]], i8 -1, i8 [[A]] -; CHECK-NEXT: [[R:%.*]] = zext i8 [[NARROW]] to i32 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND]], i32 255, i32 [[A_EXT]] ; CHECK-NEXT: ret i32 [[R]] ; %cond = icmp sgt i8 %x, 15 diff --git a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll index 44d284c..c534acd 100644 --- a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll +++ b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll @@ -224,8 +224,7 @@ define i4 @PR45762(i3 %x4) { ; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4 ; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl i4 1, [[T7]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i3 [[X4]], 0 -; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i3 0, i3 [[T4]] -; CHECK-NEXT: [[UMUL_23:%.*]] = zext i3 [[NARROW]] to i4 +; CHECK-NEXT: [[UMUL_23:%.*]] = select i1 [[TMP1]], i4 0, i4 [[T7]] ; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_23]] ; CHECK-NEXT: ret i4 [[SEL_71]] ; -- 2.7.4