From 6310a05f68ad6de50385246559dd4801b6ac925c Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Fri, 3 Apr 2020 13:04:43 -0700 Subject: [PATCH] intel/fs: Rename half() helpers to quarter(), allow index up to 3. Makes more sense considering SIMD32. Relaxing the assertion in brw_ir_fs.h will be required in order to avoid assertion failures on SNB with SIMD32 fragment shaders. Reviewed-by: Kenneth Graunke --- src/intel/compiler/brw_fs.cpp | 6 +++--- src/intel/compiler/brw_fs_builder.h | 2 +- src/intel/compiler/brw_fs_visitor.cpp | 15 ++++++++------- src/intel/compiler/brw_ir_fs.h | 5 ++--- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 0f271b0..b2234f9 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -208,7 +208,7 @@ fs_visitor::DEP_RESOLVE_MOV(const fs_builder &bld, int grf) * dependencies, and to avoid having to deal with aligning its regs to 2. */ const fs_builder ubld = bld.annotate("send dependency resolve") - .half(0); + .quarter(0); ubld.MOV(ubld.null_reg_f(), fs_reg(VGRF, grf, BRW_REGISTER_TYPE_F)); } @@ -3885,9 +3885,9 @@ fs_visitor::lower_load_payload() } else { /* Platform doesn't have COMPR4. We have to fake it */ fs_reg mov_dst = retype(dst, inst->src[i].type); - ibld.half(0).MOV(mov_dst, half(inst->src[i], 0)); + ibld.quarter(0).MOV(mov_dst, quarter(inst->src[i], 0)); mov_dst.nr += 4; - ibld.half(1).MOV(mov_dst, half(inst->src[i], 1)); + ibld.quarter(1).MOV(mov_dst, quarter(inst->src[i], 1)); } } diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 430c7d1..bdd1063 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -140,7 +140,7 @@ namespace brw { * Alias for group() with width equal to eight. */ fs_builder - half(unsigned i) const + quarter(unsigned i) const { return group(8, i); } diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 7e6bebc..0d8b0f7 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -179,10 +179,10 @@ fs_visitor::emit_interpolation_setup_gen4() if (devinfo->has_pln) { for (unsigned i = 0; i < dispatch_width / 8; i++) { - abld.half(i).ADD(half(offset(delta_xy, abld, 0), i), - half(this->pixel_x, i), xstart); - abld.half(i).ADD(half(offset(delta_xy, abld, 1), i), - half(this->pixel_y, i), ystart); + abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 0), i), + quarter(this->pixel_x, i), xstart); + abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 1), i), + quarter(this->pixel_y, i), ystart); } } else { abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart); @@ -360,9 +360,10 @@ fs_visitor::emit_interpolation_setup_gen6() for (unsigned c = 0; c < 2; c++) { for (unsigned q = 0; q < dispatch_width / 8; q++) { set_predicate(BRW_PREDICATE_NORMAL, - bld.half(q).SEL(half(offset(delta_xy[i], bld, c), q), - half(offset(centroid_delta_xy, bld, c), q), - half(offset(pixel_delta_xy, bld, c), q))); + bld.quarter(q).SEL( + quarter(offset(delta_xy[i], bld, c), q), + quarter(offset(centroid_delta_xy, bld, c), q), + quarter(offset(pixel_delta_xy, bld, c), q))); } } } diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h index af56753..f7b389d 100644 --- a/src/intel/compiler/brw_ir_fs.h +++ b/src/intel/compiler/brw_ir_fs.h @@ -276,12 +276,11 @@ is_uniform(const fs_reg ®) /** * Get the specified 8-component quarter of a register. - * XXX - Maybe come up with a less misleading name for this (e.g. quarter())? */ static inline fs_reg -half(const fs_reg ®, unsigned idx) +quarter(const fs_reg ®, unsigned idx) { - assert(idx < 2); + assert(idx < 4); return horiz_offset(reg, 8 * idx); } -- 2.7.4