From 62ec89759ab3880db52b3ddfeed48ca750f2502f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 8 Jul 2020 17:06:10 +0200 Subject: [PATCH] radv: clean up PA_SC_CLIPRECT_RULE emission Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pipeline.c | 46 ++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c1f7a0b..6cd0367 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4568,35 +4568,38 @@ radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs, radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages); } -static uint32_t -radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo) +static void +radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs, + const VkGraphicsPipelineCreateInfo *pCreateInfo) { const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info = vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT); + uint32_t cliprect_rule = 0; - if (!discard_rectangle_info) - return 0xffff; - - unsigned mask = 0; - - for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) { - /* Interpret i as a bitmask, and then set the bit in the mask if - * that combination of rectangles in which the pixel is contained - * should pass the cliprect test. */ - unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1); + if (!discard_rectangle_info) { + cliprect_rule = 0xffff; + } else { + for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) { + /* Interpret i as a bitmask, and then set the bit in + * the mask if that combination of rectangles in which + * the pixel is contained should pass the cliprect + * test. + */ + unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1); - if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT && - !relevant_subset) - continue; + if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT && + !relevant_subset) + continue; - if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT && - relevant_subset) - continue; + if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT && + relevant_subset) + continue; - mask |= 1u << i; + cliprect_rule |= 1u << i; + } } - return mask; + radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule); } static void @@ -4661,14 +4664,13 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline); radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend); radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline); + radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo); if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline)) gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess); radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); - radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo)); - pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4); assert(ctx_cs->cdw <= ctx_cs->max_dw); -- 2.7.4