From 62bb11a5a5a6e13b43afe79e678f064a74e26515 Mon Sep 17 00:00:00 2001 From: Ruijing Dong Date: Thu, 10 Mar 2022 12:13:09 -0500 Subject: [PATCH] radeonsi/vcn: Add support of array_mode for gfx11 Update array_mode for gfx11 in vcn decoder. Signed-off-by: Ruijing Dong Reviewed-by: James Zhu Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_vcn_dec.h | 5 +++++ src/gallium/drivers/radeonsi/radeon_vcn_dec.c | 6 +++++- src/gallium/drivers/radeonsi/radeon_vcn_dec.h | 1 + 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_vcn_dec.h b/src/amd/common/ac_vcn_dec.h index 7276275..888bbdd 100644 --- a/src/amd/common/ac_vcn_dec.h +++ b/src/amd/common/ac_vcn_dec.h @@ -114,6 +114,11 @@ #define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004 #define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005 +#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX10 0x00000000 +#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX9 0x00000001 +#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX8 0x00000002 +#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11 0x00000003 + #define RDECODE_H264_PROFILE_BASELINE 0x00000000 #define RDECODE_H264_PROFILE_MAIN 0x00000001 #define RDECODE_H264_PROFILE_HIGH 0x00000002 diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c index 7b585a4..db0fbeb 100755 --- a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c @@ -1788,6 +1788,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec, decode->db_aligned_height = align(dec->base.height, 64); decode->db_surf_tile_config = 0; + decode->db_array_mode = dec->addr_gfx_mode; decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; decode->dt_uv_pitch = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w; @@ -1799,7 +1800,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec, decode->dt_tiling_mode = 0; decode->dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode; - decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR; + decode->dt_array_mode = dec->addr_gfx_mode; decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced; decode->dt_surf_tile_config = 0; decode->dt_uv_surf_tile_config = 0; @@ -2730,6 +2731,8 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, } si_vid_clear_buffer(context, &dec->sessionctx); + dec->addr_gfx_mode = RDECODE_ARRAY_MODE_LINEAR; + switch (sctx->family) { case CHIP_RAVEN: case CHIP_RAVEN2: @@ -2767,6 +2770,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, case CHIP_GFX1100: case CHIP_GFX1102: dec->jpg.direct_reg = true; + dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11; break; default: RVID_ERR("VCN is not supported.\n"); diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_dec.h b/src/gallium/drivers/radeonsi/radeon_vcn_dec.h index b436083..5be8eac 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_dec.h +++ b/src/gallium/drivers/radeonsi/radeon_vcn_dec.h @@ -51,6 +51,7 @@ struct radeon_decoder { unsigned dpb_size; unsigned last_width; unsigned last_height; + unsigned addr_gfx_mode; struct pipe_screen *screen; struct radeon_winsys *ws; -- 2.7.4