From 62b3d8d10a04584c93875d9579f3d7fa273c3a2a Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Fri, 10 Jun 2022 19:13:59 -0700
Subject: [PATCH] [TableGen] const char *const x => const char x[]

---
 llvm/test/TableGen/MixedCasedMnemonic.td    | 2 +-
 llvm/test/TableGen/bare-minimum-psets.td    | 2 +-
 llvm/test/TableGen/inhibit-pset.td          | 2 +-
 llvm/utils/TableGen/AsmMatcherEmitter.cpp   | 2 +-
 llvm/utils/TableGen/CodeGenTarget.cpp       | 2 +-
 llvm/utils/TableGen/RegisterInfoEmitter.cpp | 6 +++---
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/test/TableGen/MixedCasedMnemonic.td b/llvm/test/TableGen/MixedCasedMnemonic.td
index 3dd6a21..3dc44ab 100644
--- a/llvm/test/TableGen/MixedCasedMnemonic.td
+++ b/llvm/test/TableGen/MixedCasedMnemonic.td
@@ -40,7 +40,7 @@ def :MnemonicAlias<"Insta", "aInst">;
 def :MnemonicAlias<"InstB", "BInst">;
 
 // Check that the matcher lower()s the mnemonics it matches.
-// MATCHER: static const char *const MnemonicTable =
+// MATCHER: static const char MnemonicTable[] =
 // MATCHER-NEXT: "\005ainst\005binst";
 
 // Check that aInst appears before BInst in the match table.
diff --git a/llvm/test/TableGen/bare-minimum-psets.td b/llvm/test/TableGen/bare-minimum-psets.td
index e5c842c..25e0bd2 100644
--- a/llvm/test/TableGen/bare-minimum-psets.td
+++ b/llvm/test/TableGen/bare-minimum-psets.td
@@ -48,7 +48,7 @@ def MyTarget : Target;
 // NAMESPACE-NEXT: } // end namespace TestNamespace
 
 // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
-// CHECK-NEXT:    static const char *const PressureNameTable[] = {
+// CHECK-NEXT:    static const char *PressureNameTable[] = {
 // CHECK-NEXT:      "D_32",
 // CHECK-NEXT:    };
 // CHECK-NEXT:    return PressureNameTable[Idx];
diff --git a/llvm/test/TableGen/inhibit-pset.td b/llvm/test/TableGen/inhibit-pset.td
index d9f5613..1f4f8a1 100644
--- a/llvm/test/TableGen/inhibit-pset.td
+++ b/llvm/test/TableGen/inhibit-pset.td
@@ -8,7 +8,7 @@ include "reg-with-subregs-common.td"
 def X0 : Register <"x0">;
 
 // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
-// CHECK-NEXT:    static const char *const PressureNameTable[] = {
+// CHECK-NEXT:    static const char *PressureNameTable[] = {
 // CHECK-NEXT:      "GPR32",
 // CHECK-NEXT:    };
 // CHECK-NEXT:    return PressureNameTable[Idx];
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 2c2239f..1acc2a8 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -3395,7 +3395,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
                         StringTable.GetOrAddStringOffset(LenMnemonic, false));
   }
 
-  OS << "static const char *const MnemonicTable =\n";
+  OS << "static const char MnemonicTable[] =\n";
   StringTable.EmitString(OS);
   OS << ";\n\n";
 
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 65ccb74..6c1b021 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -474,7 +474,7 @@ GetInstByName(const char *Name,
   return I->second.get();
 }
 
-static const char *const FixedInstrs[] = {
+static const char *FixedInstrs[] = {
 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
 #include "llvm/Support/TargetOpcodes.def"
     nullptr};
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 0ba6dee..3a0fa56 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -268,7 +268,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
   OS << "// Get the name of this register unit pressure set.\n"
      << "const char *" << ClassName << "::\n"
      << "getRegPressureSetName(unsigned Idx) const {\n"
-     << "  static const char *const PressureNameTable[] = {\n";
+     << "  static const char *PressureNameTable[] = {\n";
   unsigned MaxRegUnitWeight = 0;
   for (unsigned i = 0; i < NumSets; ++i ) {
     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
@@ -1264,7 +1264,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
   OS << "};\n";
 
   // Emit SubRegIndex names, skipping 0.
-  OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
+  OS << "\nstatic const char *SubRegIndexNameTable[] = { \"";
 
   for (const auto &Idx : SubRegIndices) {
     OS << Idx.getName();
@@ -1681,7 +1681,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
   OS << "ArrayRef<const char *> " << ClassName
      << "::getRegMaskNames() const {\n";
   if (!CSRSets.empty()) {
-  OS << "  static const char *const Names[] = {\n";
+    OS << "  static const char *Names[] = {\n";
     for (Record *CSRSet : CSRSets)
       OS << "    " << '"' << CSRSet->getName() << '"' << ",\n";
     OS << "  };\n";
-- 
2.7.4