From 6248d1119040d5031b248633005998b94b8024d4 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Fri, 7 May 2021 15:15:52 +0200 Subject: [PATCH] Retire TargetRegisterInfo::getSpillAlignment getSpillAlign does the same thing. --- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 6 ------ llvm/lib/CodeGen/PrologEpilogInserter.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 10 +++++----- 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 954d043..7001717 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -283,12 +283,6 @@ public: /// Return the minimum required alignment in bytes for a spill slot for /// a register of this class. - unsigned getSpillAlignment(const TargetRegisterClass &RC) const { - return getRegClassInfo(RC).SpillAlignment / 8; - } - - /// Return the minimum required alignment in bytes for a spill slot for - /// a register of this class. Align getSpillAlign(const TargetRegisterClass &RC) const { return Align(getRegClassInfo(RC).SpillAlignment / 8); } diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 13d3a05..cccab5f 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -436,7 +436,7 @@ static void assignCalleeSavedSpillSlots(MachineFunction &F, unsigned Size = RegInfo->getSpillSize(*RC); if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) { // Nope, just spill it anywhere convenient. - Align Alignment(RegInfo->getSpillAlignment(*RC)); + Align Alignment = RegInfo->getSpillAlign(*RC); // We may not be able to satisfy the desired alignment specification of // the TargetRegisterClass if the stack alignment is smaller. Use the // min. diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index edb8d7f..1d722a7 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -521,7 +521,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (NeedsArgAlign && Subtarget.hasV60Ops()) { LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); - Align VecAlign(HRI.getSpillAlignment(Hexagon::HvxVRRegClass)); + Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); LargestAlignSeen = std::max(LargestAlignSeen, VecAlign); MFI.ensureMaxAlignment(LargestAlignSeen); } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 26fc093..f14eaac 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1022,7 +1022,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { return true; }; - auto UseAligned = [&] (const MachineInstr &MI, unsigned NeedAlign) { + auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) { if (MI.memoperands().empty()) return false; return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) { @@ -1086,7 +1086,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { const MachineOperand &BaseOp = MI.getOperand(1); assert(BaseOp.getSubReg() == 0); int Offset = MI.getOperand(2).getImm(); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai; BuildMI(MBB, MI, DL, get(NewOpc), DstReg) @@ -1102,7 +1102,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { assert(BaseOp.getSubReg() == 0); int Offset = MI.getOperand(2).getImm(); unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai; BuildMI(MBB, MI, DL, get(NewOpc), @@ -1124,7 +1124,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { const MachineOperand &BaseOp = MI.getOperand(0); assert(BaseOp.getSubReg() == 0); int Offset = MI.getOperand(1).getImm(); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai; BuildMI(MBB, MI, DL, get(NewOpc)) @@ -1141,7 +1141,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { assert(BaseOp.getSubReg() == 0); int Offset = MI.getOperand(1).getImm(); unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai; BuildMI(MBB, MI, DL, get(NewOpc)) -- 2.7.4