From 61c76239491374472580e174a87c00f5bcbb93ed Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Wed, 22 Nov 2006 16:41:29 +0000 Subject: [PATCH] spe.md (SPE64): New mode macro. * config/rs6000/spe.md (SPE64): New mode macro. (mov_sidf_e500_subreg0): Change to mov_si_e500_subreg0. Add memory load. (mov_si_e500_subreg0_2): New. (mov_sidf_e500_subreg4): Change to mov_si_e500_subreg4. Add memory load. (mov_si_e500_subreg4_2): New. * config/rs6000/predicates.md (input_operand): Do not allow invalid E500 subregs. (rs6000_nonimmediate_operand): Check for invalid E500 subregs also if TARGET_SPE. * config/rs6000/rs6000.c (invalid_e500_subreg): Check for subregs involving DFmode if TARGET_E500_DOUBLE. Check for subregs involving vector modes if TARGET_SPE. From-SVN: r119094 --- gcc/ChangeLog | 17 ++++++++++++++++ gcc/config/rs6000/predicates.md | 8 +++++++- gcc/config/rs6000/rs6000.c | 31 +++++++++++++++++++--------- gcc/config/rs6000/spe.md | 45 ++++++++++++++++++++++++++++++++--------- 4 files changed, 80 insertions(+), 21 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5555cc4..31edafe 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2006-11-22 Joseph Myers + + * config/rs6000/spe.md (SPE64): New mode macro. + (mov_sidf_e500_subreg0): Change to mov_si_e500_subreg0. Add + memory load. + (mov_si_e500_subreg0_2): New. + (mov_sidf_e500_subreg4): Change to mov_si_e500_subreg4. Add + memory load. + (mov_si_e500_subreg4_2): New. + * config/rs6000/predicates.md (input_operand): Do not allow + invalid E500 subregs. + (rs6000_nonimmediate_operand): Check for invalid E500 subregs also + if TARGET_SPE. + * config/rs6000/rs6000.c (invalid_e500_subreg): Check for subregs + involving DFmode if TARGET_E500_DOUBLE. Check for subregs + involving vector modes if TARGET_SPE. + 2006-11-22 Kaz Kojima Revert diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index f8e00ff..2ff0ba7 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -722,6 +722,12 @@ && easy_vector_constant (op, mode)) return 1; + /* Do not allow invalid E500 subregs. */ + if ((TARGET_E500_DOUBLE || TARGET_SPE) + && GET_CODE (op) == SUBREG + && invalid_e500_subreg (op, mode)) + return 0; + /* For floating-point or multi-word mode, the only remaining valid type is a register. */ if (SCALAR_FLOAT_MODE_P (mode) @@ -756,7 +762,7 @@ (define_predicate "rs6000_nonimmediate_operand" (match_code "reg,subreg,mem") { - if (TARGET_E500_DOUBLE + if ((TARGET_E500_DOUBLE || TARGET_SPE) && GET_CODE (op) == SUBREG && invalid_e500_subreg (op, mode)) return 0; diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index dc80f9f..f8e58fb 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2713,18 +2713,29 @@ build_mask64_2_operands (rtx in, rtx *out) bool invalid_e500_subreg (rtx op, enum machine_mode mode) { - /* Reject (subreg:SI (reg:DF)). */ - if (GET_CODE (op) == SUBREG - && mode == SImode - && REG_P (SUBREG_REG (op)) - && GET_MODE (SUBREG_REG (op)) == DFmode) - return true; + if (TARGET_E500_DOUBLE) + { + /* Reject (subreg:SI (reg:DF)). */ + if (GET_CODE (op) == SUBREG + && mode == SImode + && REG_P (SUBREG_REG (op)) + && GET_MODE (SUBREG_REG (op)) == DFmode) + return true; - /* Reject (subreg:DF (reg:DI)). */ - if (GET_CODE (op) == SUBREG - && mode == DFmode + /* Reject (subreg:DF (reg:DI)). */ + if (GET_CODE (op) == SUBREG + && mode == DFmode + && REG_P (SUBREG_REG (op)) + && GET_MODE (SUBREG_REG (op)) == DImode) + return true; + } + + if (TARGET_SPE + && GET_CODE (op) == SUBREG + && mode == SImode && REG_P (SUBREG_REG (op)) - && GET_MODE (SUBREG_REG (op)) == DImode) + && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))) + && SUBREG_BYTE (op) != 4) return true; return false; diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 02e13c6..7d05e08 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -32,6 +32,9 @@ (E500_CR_IOR_COMPARE 1012) ]) +;; Modes using a 64-bit register. +(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI]) + (define_insn "*negsf2_gpr" [(set (match_operand:SF 0 "gpc_reg_operand" "=r") (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] @@ -2241,17 +2244,39 @@ }" [(set_attr "length" "8,8")]) -(define_insn "*mov_sidf_e500_subreg0" - [(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 0) - (match_operand:SI 1 "register_operand" "r"))] - "TARGET_E500_DOUBLE" - "evmergelo %0,%1,%0") +(define_insn "*mov_si_e500_subreg0" + [(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,&r") 0) + (match_operand:SI 1 "input_operand" "r,m"))] + "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)" + "@ + evmergelo %0,%1,%0 + evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0") + +;; ??? Could use evstwwe for memory stores in some cases, depending on +;; the offset. +(define_insn "*mov_si_e500_subreg0_2" + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + (subreg:SI (match_operand:SPE64 1 "register_operand" "+r,&r") 0))] + "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)" + "@ + evmergehi %0,%0,%1 + evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0") -(define_insn "*mov_sidf_e500_subreg4" - [(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 4) - (match_operand:SI 1 "register_operand" "r"))] - "TARGET_E500_DOUBLE" - "mr %0,%1") +(define_insn "*mov_si_e500_subreg4" + [(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,r") 4) + (match_operand:SI 1 "input_operand" "r,m"))] + "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)" + "@ + mr %0,%1 + {l%U1%X1|lwz%U1%X1} %0,%1") + +(define_insn "*mov_si_e500_subreg4_2" + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + (subreg:SI (match_operand:SPE64 1 "register_operand" "r,r") 4))] + "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)" + "@ + mr %0,%1 + {st%U0%X0|stw%U0%X0} %1,%0") ;; FIXME: Allow r=CONST0. (define_insn "*movdf_e500_double" -- 2.7.4