From 61b396b911969ddb018db8b8d79a501b6b1920e3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 20 Aug 2021 13:51:10 -0400 Subject: [PATCH] drm/amdgpu/pm/smu_v13.0: convert IP version checking MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index a0e50f2..08f3cc8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -89,12 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu) if (amdgpu_sriov_vf(adev)) return 0; - switch (adev->asic_type) { - case CHIP_ALDEBARAN: + switch (adev->ip_versions[MP1_HWIP]) { + case IP_VERSION(13, 0, 2): chip_name = "aldebaran"; break; default: - dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type); + dev_err(adev->dev, "Unsupported IP version 0x%x\n", + adev->ip_versions[MP1_HWIP]); return -EINVAL; } @@ -210,15 +211,17 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) smu_minor = (smu_version >> 8) & 0xff; smu_debug = (smu_version >> 0) & 0xff; - switch (smu->adev->asic_type) { - case CHIP_ALDEBARAN: + switch (smu->adev->ip_versions[MP1_HWIP]) { + case IP_VERSION(13, 0, 2): smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; break; - case CHIP_YELLOW_CARP: + case IP_VERSION(13, 0, 1): + case IP_VERSION(13, 0, 3): smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP; break; default: - dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); + dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n", + smu->adev->ip_versions[MP1_HWIP]); smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV; break; } @@ -740,8 +743,9 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable) int ret = 0; struct amdgpu_device *adev = smu->adev; - switch (adev->asic_type) { - case CHIP_YELLOW_CARP: + switch (adev->ip_versions[MP1_HWIP]) { + case IP_VERSION(13, 0, 1): + case IP_VERSION(13, 0, 3): if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) return 0; if (enable) -- 2.7.4