From 61a7928dde74b36b1c3a75eb17c178e70182e045 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Thu, 28 Jul 2016 16:58:31 +0000
Subject: [PATCH] [AArch64][GlobalISel] Select GPR G_AND.

llvm-svn: 277002
---
 .../Target/AArch64/AArch64InstructionSelector.cpp  |  5 +++
 .../AArch64/GlobalISel/arm64-instructionselect.mir | 51 ++++++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 26b574a..db8bfc9 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -52,6 +52,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
       switch (GenericOpc) {
       case TargetOpcode::G_OR:
         return AArch64::ORRWrr;
+      case TargetOpcode::G_AND:
+        return AArch64::ANDWrr;
       case TargetOpcode::G_ADD:
         return AArch64::ADDWrr;
       default:
@@ -61,6 +63,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
       switch (GenericOpc) {
       case TargetOpcode::G_OR:
         return AArch64::ORRXrr;
+      case TargetOpcode::G_AND:
+        return AArch64::ANDXrr;
       case TargetOpcode::G_ADD:
         return AArch64::ADDXrr;
       default:
@@ -105,6 +109,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
 
   switch (I.getOpcode()) {
   case TargetOpcode::G_OR:
+  case TargetOpcode::G_AND:
   case TargetOpcode::G_ADD: {
     DEBUG(dbgs() << "AArch64: Selecting: binop\n");
 
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
index 67851e5..e279ada 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -14,6 +14,9 @@
   define void @or_s32_gpr() { ret void }
   define void @or_s64_gpr() { ret void }
 
+  define void @and_s32_gpr() { ret void }
+  define void @and_s64_gpr() { ret void }
+
 ...
 
 ---
@@ -112,3 +115,51 @@ body:             |
     %0(64) = COPY %x0
     %1(64) = G_OR s64 %0, %0
 ...
+
+---
+# Same as add_s32_gpr, for G_AND operations.
+# CHECK-LABEL: name: and_s32_gpr
+name:            and_s32_gpr
+isSSA:           true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %1 = ANDWrr %0, %0
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(32) = COPY %w0
+    %1(32) = G_AND s32 %0, %0
+...
+
+---
+# Same as add_s64_gpr, for G_AND operations.
+# CHECK-LABEL: name: and_s64_gpr
+name:            and_s64_gpr
+isSSA:           true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = ANDXrr %0, %0
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0(64) = COPY %x0
+    %1(64) = G_AND s64 %0, %0
+...
-- 
2.7.4