From 616ae7bf7dbb1edd5c2c8936a009d639e3268e4d Mon Sep 17 00:00:00 2001 From: Shijie Zhang Date: Fri, 30 Mar 2012 21:36:39 +0800 Subject: [PATCH] intel_mid_osip: update intel osnib and oshob driver BZ: 28905 Base on current IPC driver framework, it is not suitable to put OSNIB and OSHOB access code inside IPC bus driver. So we move it into intel_mid_osip driver, to make it more clear in logic. Change-Id: I1aaf95f44bd85b524dde52b0e2542a9d6f811c3e Signed-off-by: Shijie Zhang Reviewed-on: http://android.intel.com:8080/41846 Reviewed-by: Yang, Bin Reviewed-by: Du, Alek Reviewed-by: Gross, Mark Tested-by: Romieu, Benoit Reviewed-by: buildbot Tested-by: buildbot --- arch/x86/include/asm/intel_mid_osip.h | 9 + arch/x86/include/asm/intel_scu_ipc.h | 8 - arch/x86/platform/intel-mid/intel-mid.c | 5 + drivers/platform/x86/Makefile | 1 - drivers/platform/x86/intel_mid_osip.c | 165 ++++++++++++++- drivers/platform/x86/intel_scu_ipc.c | 94 --------- drivers/platform/x86/intel_scu_ipcutil.c | 350 ------------------------------- drivers/watchdog/intel_scu_watchdog.c | 3 +- 8 files changed, 173 insertions(+), 462 deletions(-) create mode 100644 arch/x86/include/asm/intel_mid_osip.h delete mode 100644 drivers/platform/x86/intel_scu_ipcutil.c diff --git a/arch/x86/include/asm/intel_mid_osip.h b/arch/x86/include/asm/intel_mid_osip.h new file mode 100644 index 0000000..4ff33a9 --- /dev/null +++ b/arch/x86/include/asm/intel_mid_osip.h @@ -0,0 +1,9 @@ +#ifndef _ASM_X86_INTEL_MID_OSIP_H_ +#define _ASM_X86_INTEL_MID_OSIP_H_ + +extern int intel_mid_osip_read_oshob(u8 *data, int len, int offset); +extern int intel_mid_osip_write_osnib(u8 *data, int len, int offset, u32 mask); +extern int intel_mid_osip_write_osnib_rr(u8 rr); +extern int intel_mid_osip_read_osnib_rr(u8 *rr); + +#endif diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h index abdde5d..e78cb98 100644 --- a/arch/x86/include/asm/intel_scu_ipc.h +++ b/arch/x86/include/asm/intel_scu_ipc.h @@ -53,14 +53,6 @@ int intel_scu_ipc_medfw_prepare(void __user *arg); int intel_scu_ipc_read_mip(u8 *data, int len, int offset, int issigned); int intel_scu_ipc_write_umip(u8 *data, int len, int offset); -/* OSHOB-OS Handoff Buffer read */ -int intel_scu_ipc_read_oshob(u8 *data, int len, int offset); -/* OSNIB-OS No Init Buffer write */ -#define OSNIB_OFFSET 0x0C -int intel_scu_ipc_write_osnib(u8 *data, int len, int offset, u32 mask); -int intel_scu_ipc_write_osnib_rr(u8 rr); -int intel_scu_ipc_read_osnib_rr(u8 *rr); - /* Penwell has 4 osc clocks */ #define OSC_CLK_AUDIO 0 /* Audio */ #define OSC_CLK_CAM0 1 /* Primary camera */ diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c index 04b623a..baee30e 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -563,6 +563,11 @@ static int __init intel_scu_ipc_subdev_init(void) .name = "intel_scu_mip", .bus_id = IPC_SCU, }, + + [2] = { + .name = "intel_mid_osip", + .bus_id = IPC_SCU, + }, }; for (i = 0; i < ARRAY_SIZE(info); i++) { diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile index d942eef..216dc89 100644 --- a/drivers/platform/x86/Makefile +++ b/drivers/platform/x86/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_TOPSTAR_LAPTOP) += topstar-laptop.o obj-$(CONFIG_ACPI_TOSHIBA) += toshiba_acpi.o obj-$(CONFIG_TOSHIBA_BT_RFKILL) += toshiba_bluetooth.o obj-$(CONFIG_INTEL_SCU_IPC) += intel_scu_ipc.o intel_scu_pmic.o intel_scu_mip.o -obj-$(CONFIG_INTEL_SCU_IPC_UTIL) += intel_scu_ipcutil.o obj-$(CONFIG_INTEL_MFLD_THERMAL) += intel_mid_thermal.o obj-$(CONFIG_RAR_REGISTER) += intel_rar_register.o obj-$(CONFIG_INTEL_IPS) += intel_ips.o diff --git a/drivers/platform/x86/intel_mid_osip.c b/drivers/platform/x86/intel_mid_osip.c index 3381c15..189b2c1 100644 --- a/drivers/platform/x86/intel_mid_osip.c +++ b/drivers/platform/x86/intel_mid_osip.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include /* change to "loop0" and use losetup for safe testing */ #define OSIP_BLKDEVICE "mmcblk0" @@ -68,6 +70,127 @@ struct OSIP_header { /* os image profile */ force shuts down */ static int force_shutdown_occured; +#define OSHOB_SIZE 60 +#define OSNIB_SIZE 32 +#define IPCMSG_GET_HOBADDR 0xE5 + +int intel_mid_osip_read_oshob(u8 *data, int len, int offset) +{ + int ret, i; + u32 oshob_base; + void __iomem *oshob_addr; + + ret = intel_scu_ipc_command(IPCMSG_GET_HOBADDR, 0, NULL, 0, + &oshob_base, 1); + if (ret < 0) { + pr_err("ipc_read_oshob failed!!\n"); + goto exit; + } + + pr_info("OSHOB addr values is %x\n", oshob_base); + + oshob_addr = ioremap_nocache(oshob_base, OSHOB_SIZE); + if (!oshob_addr) { + pr_err("ioremap failed!\n"); + ret = -ENOMEM; + goto exit; + } else { + u8 *ptr = data; + for (i = 0; i < len; i = i+1) { + *ptr = readb(oshob_addr + offset + i); + pr_info("addr=%8x, offset=%2x, value=%2x\n", + (u32)(oshob_addr + i), + offset + i, *ptr); + ptr++; + } + } + + iounmap(oshob_addr); +exit: + return ret; +} +EXPORT_SYMBOL_GPL(intel_mid_osip_read_oshob); + +#define IPCMSG_WRITE_OSNIB 0xE4 +#define POSNIBW_OFFSET 0x34 + +int intel_mid_osip_write_osnib(u8 *data, int len, int offset, u32 mask) +{ + int i; + int ret = 0; + u32 posnibw, oshob_base; + void __iomem *oshob_addr, *osnibw_addr; + + ret = intel_scu_ipc_command(IPCMSG_GET_HOBADDR, 0, NULL, 0, + &oshob_base, 1); + if (ret < 0) { + pr_err("ipc_get_hobaddr failed!!\n"); + goto exit; + } + + pr_info("OSHOB addr values is %x\n", oshob_base); + + intel_scu_ipc_lock(); + + oshob_addr = ioremap_nocache(oshob_base, OSHOB_SIZE); + if (!oshob_addr) { + pr_err("ioremap failed!\n"); + ret = -ENOMEM; + goto exit; + } + + posnibw = readl(oshob_addr + POSNIBW_OFFSET); + if (posnibw == 0) { /* workaround here for BZ 2914 */ + posnibw = 0xFFFF3400; + pr_err("ERR: posnibw from oshob is 0, manually set it here\n"); + } + + pr_info("POSNIB: %x\n", posnibw); + + osnibw_addr = ioremap_nocache(posnibw, OSNIB_SIZE); + if (!osnibw_addr) { + pr_err("ioremap failed!\n"); + ret = -ENOMEM; + goto unmap_oshob_addr; + } + + for (i = 0; i < len; i++) + writeb(*(data + i), (osnibw_addr + offset + i)); + + ret = intel_scu_ipc_raw_cmd(IPCMSG_WRITE_OSNIB, 0, NULL, 0, NULL, + 0, 0, mask); + if (ret < 0) + pr_err("ipc_write_osnib failed!!\n"); + + iounmap(osnibw_addr); + +unmap_oshob_addr: + iounmap(oshob_addr); +exit: + intel_scu_ipc_unlock(); + + return ret; +} +EXPORT_SYMBOL_GPL(intel_mid_osip_write_osnib); + +#define OSNIB_OFFSET 0x0C +#define OSNIB_RR_OFFSET OSNIB_OFFSET +#define OSNIB_RR_MASK 0x00000001 + +int intel_mid_osip_write_osnib_rr(u8 rr) +{ + return intel_mid_osip_write_osnib(&rr, 1, + OSNIB_RR_OFFSET - OSNIB_OFFSET, + OSNIB_RR_MASK); +} +EXPORT_SYMBOL_GPL(intel_mid_osip_write_osnib_rr); + +int intel_mid_osip_read_osnib_rr(u8 *rr) +{ + return intel_mid_osip_read_oshob(rr, 1, OSNIB_RR_OFFSET); +} +EXPORT_SYMBOL_GPL(intel_mid_osip_read_osnib_rr); + int mmcblk0_match(struct device *dev, void *data) { if (strcmp(dev_name(dev), OSIP_BLKDEVICE) == 0) @@ -235,15 +358,15 @@ static int osip_reboot_notifier_call(struct notifier_block *notifier, "plugged in\n", __func__); pr_info("charger connected ...\n"); #ifdef DEBUG - intel_scu_ipc_read_osnib_rr(&rbt_reason); + intel_mid_osip_read_osnib_rr(&rbt_reason); #endif - ret_ipc = intel_scu_ipc_write_osnib_rr( + ret_ipc = intel_mid_osip_write_osnib_rr( SIGNED_COS_ATTR); if (ret_ipc < 0) pr_err("%s cannot write reboot reason" " in OSNIB\n", __func__); #ifdef DEBUG - intel_scu_ipc_read_osnib_rr(&rbt_reason); + intel_mid_osip_read_osnib_rr(&rbt_reason); #endif } else { pr_warn("[SHTDWN] %s, Shutdown without charger" @@ -260,9 +383,9 @@ static int osip_reboot_notifier_call(struct notifier_block *notifier, pr_warn("[SHTDWN] %s, invalidating osip and rebooting into " "Recovery\n", __func__); #ifdef DEBUG - intel_scu_ipc_read_osnib_rr(&rbt_reason); + intel_mid_osip_read_osnib_rr(&rbt_reason); #endif - ret_ipc = intel_scu_ipc_write_osnib_rr(SIGNED_RECOVERY_ATTR); + ret_ipc = intel_mid_osip_write_osnib_rr(SIGNED_RECOVERY_ATTR); if (ret_ipc < 0) pr_err("%s cannot write reboot reason in OSNIB\n", __func__); @@ -271,7 +394,7 @@ static int osip_reboot_notifier_call(struct notifier_block *notifier, } else if (0 == strncmp(cmd, "bootloader", 11)) { pr_warn("[SHTDWN] %s, invalidating osip and rebooting into " "Fastboot\n", __func__); - ret_ipc = intel_scu_ipc_write_osnib_rr(SIGNED_POS_ATTR); + ret_ipc = intel_mid_osip_write_osnib_rr(SIGNED_POS_ATTR); if (ret_ipc < 0) pr_err("%s cannot write reboot reason in OSNIB\n", __func__); @@ -279,7 +402,7 @@ static int osip_reboot_notifier_call(struct notifier_block *notifier, } else if (0 == strncmp(cmd, "android", 8)) { pr_warn("[SHTDWN] %s, restoring OSIP and rebooting into " "Android\n", __func__); - ret_ipc = intel_scu_ipc_write_osnib_rr(SIGNED_MOS_ATTR); + ret_ipc = intel_mid_osip_write_osnib_rr(SIGNED_MOS_ATTR); if (ret_ipc < 0) pr_err("%s cannot write reboot reason in OSNIB\n", __func__); @@ -542,17 +665,43 @@ static void remove_debugfs_files(void) } #endif +static int __devinit intel_osip_probe(struct ipc_device *ipcdev) +{ + return 0; +} + +static int __devexit intel_osip_remove(struct ipc_device *ipcdev) +{ + return 0; +} + +static struct ipc_driver osip_driver = { + .driver = { + .name = "intel_mid_osip", + .owner = THIS_MODULE, + }, + .probe = intel_osip_probe, + .remove = __devexit_p(intel_osip_remove), +}; + static int __init osip_init(void) { + if (intel_mid_identify_cpu() == 0) + return -ENODEV; + if (register_reboot_notifier(&osip_reboot_notifier)) pr_warning("osip: unable to register reboot notifier"); + create_debugfs_files(); - return 0; + + return ipc_driver_register(&osip_driver); } + static void __exit osip_exit(void) { unregister_reboot_notifier(&osip_reboot_notifier); remove_debugfs_files(); + ipc_driver_unregister(&osip_driver); } module_init(osip_init); module_exit(osip_exit); diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c index 09180fe..666aac0 100644 --- a/drivers/platform/x86/intel_scu_ipc.c +++ b/drivers/platform/x86/intel_scu_ipc.c @@ -1590,100 +1590,6 @@ static void intel_scu_sysfs_remove(struct pci_dev *dev) sysfs_remove_group(&dev->dev.kobj, &intel_scu_ipc_attr_group); } -#define OSHOB_SIZE 60 -#define OSNIB_SIZE 32 -#define IPCMSG_GET_HOBADDR 0xE5 - -int intel_scu_ipc_read_oshob(u8 *data, int len, int offset) -{ - int ret, i; - u32 oshob_base; - void __iomem *oshob_addr; - ret = intel_scu_ipc_command(IPCMSG_GET_HOBADDR, 0, - NULL, 0, &oshob_base, 1); - if (ret < 0) { - pr_err("ipc_read_oshob failed!!\n"); - goto exit; - } - pr_info("OSHOB addr values is %x\n", oshob_base); - oshob_addr = ioremap_nocache(oshob_base, OSHOB_SIZE); - if (!oshob_addr) { - pr_err("ioremap failed!\n"); - ret = -ENOMEM; - goto exit; - } else { - u8 *ptr = data; - for (i = 0; i < len; i = i+1) { - *ptr = readb(oshob_addr + offset + i); - pr_info("addr=%8x, offset=%2x, value=%2x\n", - (u32)(oshob_addr+i), offset+i, *ptr); - ptr++; - } - } - iounmap(oshob_addr); -exit: - return 0; -} -EXPORT_SYMBOL_GPL(intel_scu_ipc_read_oshob); - -#define IPCMSG_WRITE_OSNIB 0xE4 -#define POSNIBW_OFFSET 0x34 - -int intel_scu_ipc_write_osnib(u8 *data, int len, int offset, u32 mask) -{ - int ret = 0; - int i; - u32 posnibw; - u32 oshob_base; - void __iomem *oshob_addr; - void __iomem *osnibw_addr; - - ret = intel_scu_ipc_command(IPCMSG_GET_HOBADDR, 0, - NULL, 0, &oshob_base, 1); - if (ret < 0) { - pr_err("ipc_get_hobaddr failed!!\n"); - goto exit; - } - pr_info("OSHOB addr values is %x\n", oshob_base); - - mutex_lock(&ipclock); - - oshob_addr = ioremap_nocache(oshob_base, OSHOB_SIZE); - if (!oshob_addr) { - pr_err("ioremap failed!\n"); - ret = -ENOMEM; - goto exit; - } - posnibw = readl(oshob_addr + POSNIBW_OFFSET); - if (posnibw == 0) { /* workaround here for BZ 2914 */ - posnibw = 0xFFFF3400; - pr_err("ERR: posnibw from oshob is 0, manually set it here\n"); - } - pr_info("POSNIB: %x\n", posnibw); - osnibw_addr = ioremap_nocache(posnibw, OSNIB_SIZE); - if (!osnibw_addr) { - pr_err("ioremap failed!\n"); - ret = -ENOMEM; - goto unmap_oshob_addr; - } - for (i = 0; i < len; i++) - writeb(*(data + i), (osnibw_addr + offset + i)); - - writel(mask, ipcdev.ipc_base + IPC_SPTR_ADDR); - - ipc_command(IPCMSG_WRITE_OSNIB); - ret = ipc_wait_interrupt(); - if (ret < 0) - pr_err("ipc_write_osnib failed!!\n"); - -unmap_oshob_addr: - iounmap(oshob_addr); -exit: - mutex_unlock(&ipclock); - return ret; -} -EXPORT_SYMBOL_GPL(intel_scu_ipc_write_osnib); - int intel_scu_ipc_osc_clk(u8 clk, unsigned int khz) { /* SCU IPC COMMAND(osc clk on/off) definition: diff --git a/drivers/platform/x86/intel_scu_ipcutil.c b/drivers/platform/x86/intel_scu_ipcutil.c deleted file mode 100644 index a798d8e..0000000 --- a/drivers/platform/x86/intel_scu_ipcutil.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism - * - * (C) Copyright 2008-2010 Intel Corporation - * Author: Sreedhara DS (sreedhara.ds@intel.com) - * (C) Copyright 2010 Intel Corporation - * Author: Sudha Krishnakumar (sudha.krishnakumar@intel.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; version 2 - * of the License. - * - * This driver provides ioctl interfaces to call intel scu ipc driver api - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX_FW_SIZE 264192 - -/* ioctl commnds */ -#define INTEL_SCU_IPC_REGISTER_READ 0 -#define INTEL_SCU_IPC_REGISTER_WRITE 1 -#define INTEL_SCU_IPC_REGISTER_UPDATE 2 -#define INTEL_SCU_IPC_FW_UPDATE 0xA2 -#define INTEL_SCU_IPC_MEDFIELD_FW_UPDATE 0xA3 -#define INTEL_SCU_IPC_FW_REVISION_GET 0xB0 -#define INTEL_SCU_IPC_READ_RR_FROM_OSNIB 0xC1 -#define INTEL_SCU_IPC_WRITE_RR_TO_OSNIB 0xC2 -#define INTEL_SCU_IPC_READ_VBATTCRIT 0xC4 -#define INTEL_SCU_IPC_WRITE_ALARM_FLAG_TO_OSNIB 0xC5 - -#define OSHOB_PMIT_OFFSET 0x0000002c -#define OSNIB_RR_OFFSET OSNIB_OFFSET -#define OSNIB_WD_OFFSET (OSNIB_OFFSET + 1) -#define OSNIB_ALARM_OFFSET (OSNIB_OFFSET + 2) -#define OSNIB_WAKESRC_OFFSET (OSNIB_OFFSET + 3) -#define OSNIB_RESETIRQ1_OFFSET (OSNIB_OFFSET + 4) -#define OSNIB_RESETIRQ2_OFFSET (OSNIB_OFFSET + 5) -#define OSNIB_RR_MASK 0x00000001 -#define OSNIB_WD_MASK 0x00000002 -#define OSNIB_ALARM_MASK 0x00000004 -#define OSNIB_WAKESRC_MASK 0x00000008 -#define OSNIB_RESETIRQ1_MASK 0x00000010 -#define OSNIB_RESETIRQ2_MASK 0x00000020 -#define PMIT_RESETIRQ1_OFFSET 14 -#define PMIT_RESETIRQ2_OFFSET 15 - -#define DUMP_OSNIB - -struct scu_ipc_data { - u32 count; /* No. of registers */ - u16 addr[5]; /* Register addresses */ - u8 data[5]; /* Register data */ - u8 mask; /* Valid for read-modify-write */ -}; - -struct scu_ipc_version { - u32 count; /* length of version info */ - u8 data[16]; /* version data */ -}; - -/** - * scu_reg_access - implement register access ioctls - * @cmd: command we are doing (read/write/update) - * @data: kernel copy of ioctl data - * - * Allow the user to perform register accesses on the SCU via the - * kernel interface - */ - -static int scu_reg_access(u32 cmd, struct scu_ipc_data *data) -{ - int ret; - - if (data->count == 0 || data->count > 5) - return -EINVAL; - - switch (cmd) { - case INTEL_SCU_IPC_REGISTER_READ: - ret = intel_scu_ipc_readv(data->addr, data->data, data->count); - break; - case INTEL_SCU_IPC_REGISTER_WRITE: - ret = intel_scu_ipc_writev(data->addr, data->data, data->count); - break; - case INTEL_SCU_IPC_REGISTER_UPDATE: - ret = intel_scu_ipc_update_register(data->addr[0], - data->data[0], - data->mask); - break; - default: - return -ENOTTY; - } - return ret; -} - -/** - * scu_ipc_ioctl - control ioctls for the SCU - * @fp: file handle of the SCU device - * @cmd: ioctl coce - * @arg: pointer to user passed structure - * - * Support the I/O and firmware flashing interfaces of the SCU - */ -static long scu_ipc_ioctl(struct file *fp, unsigned int cmd, - unsigned long arg) -{ - int ret = -EINVAL; - struct scu_ipc_data data; - void __user *argp = (void __user *)arg; - int platform; - - /* Only IOCTL cmd allowed to pass through without capability check */ - /* is getting fw version info, all others need to check to prevent */ - /* arbitrary access to all sort of bit of the hardware exposed here*/ - - if (cmd != INTEL_SCU_IPC_FW_REVISION_GET && !capable(CAP_SYS_RAWIO)) - return -EPERM; - - platform = intel_mid_identify_cpu(); - switch (cmd) { - case INTEL_SCU_IPC_FW_UPDATE: - { - if (platform == INTEL_MID_CPU_CHIP_LINCROFT) { - u8 *fwbuf = kmalloc(MAX_FW_SIZE, GFP_KERNEL); - if (fwbuf == NULL) - return -ENOMEM; - if (copy_from_user(fwbuf, (u8 *)arg, MAX_FW_SIZE)) { - kfree(fwbuf); - return -EFAULT; - } - ret = intel_scu_ipc_mrstfw_update(fwbuf, MAX_FW_SIZE); - kfree(fwbuf); - } - break; - } - case INTEL_SCU_IPC_READ_RR_FROM_OSNIB: - { - u8 reboot_reason; - ret = intel_scu_ipc_read_osnib_rr(&reboot_reason); - if (ret < 0) - return ret; - ret = copy_to_user(argp, &reboot_reason, 1); - break; - } - case INTEL_SCU_IPC_WRITE_RR_TO_OSNIB: - { - u8 data; - - ret = copy_from_user(&data, (u8 *)arg, 1); - if (ret < 0) { - pr_err("copy from user failed!!\n"); - return ret; - } - ret = intel_scu_ipc_write_osnib_rr(data); - break; - } - case INTEL_SCU_IPC_WRITE_ALARM_FLAG_TO_OSNIB: - { - u8 flag, data; - ret = copy_from_user(&flag, (u8 *)arg, 1); - if (ret < 0) { - pr_err("copy from user failed!!\n"); - return ret; - } - ret = intel_scu_ipc_read_oshob(&data, 1, OSNIB_ALARM_OFFSET); - if (ret < 0) - return ret; - if (flag) - data = data | 0x1; /* set alarm flag */ - else - data = data & 0xFE; /* clear alarm flag */ - ret = intel_scu_ipc_write_osnib(&data, 1, 2, OSNIB_ALARM_MASK); - break; - } - case INTEL_SCU_IPC_READ_VBATTCRIT: - { - u32 value; - - pr_debug("cmd = INTEL_SCU_IPC_READ_VBATTCRIT"); - ret = intel_scu_ipc_read_mip((u8 *)&value, 4, 0x318, 1); - if (ret < 0) - return ret; - pr_debug("VBATTCRIT VALUE = %x\n", value); - ret = copy_to_user(argp, &value, 4); - break; - } - case INTEL_SCU_IPC_MEDFIELD_FW_UPDATE: - { - if (platform == INTEL_MID_CPU_CHIP_PENWELL) { - ret = intel_scu_ipc_medfw_prepare(argp); - - if (ret < 0) { - pr_err("ipc_device_medfw_upgrade failed!!\n"); - return ret; - } - } - break; - } - case INTEL_SCU_IPC_FW_REVISION_GET: - { - struct scu_ipc_version version; - - if (copy_from_user(&version, argp, sizeof(u32))) - return -EFAULT; - - if (version.count > 16) - return -EINVAL; - - ret = intel_scu_ipc_command(IPCMSG_FW_REVISION, 0, - NULL, 0, (u32 *)version.data, 4); - if (ret < 0) - return ret; - - if (copy_to_user(argp + sizeof(u32), - version.data, version.count)) - ret = -EFAULT; - break; - } - default: - if (copy_from_user(&data, argp, sizeof(struct scu_ipc_data))) - return -EFAULT; - ret = scu_reg_access(cmd, &data); - if (ret < 0) - return ret; - if (copy_to_user(argp, &data, sizeof(struct scu_ipc_data))) - return -EFAULT; - return 0; - } - - return ret; -} - -/* - * This writes the reboot reason in the OSNIB (factor and avoid any overlap) - */ -int intel_scu_ipc_write_osnib_rr(u8 rr) -{ - return intel_scu_ipc_write_osnib(&rr, 1, OSNIB_RR_OFFSET-OSNIB_OFFSET, - OSNIB_RR_MASK); -} -EXPORT_SYMBOL_GPL(intel_scu_ipc_write_osnib_rr); - -/* - * This reads the reboot reason from the OSNIB (factor) - */ -int intel_scu_ipc_read_osnib_rr(u8 *rr) -{ - return intel_scu_ipc_read_oshob(rr, 1, OSNIB_RR_OFFSET); -} -EXPORT_SYMBOL_GPL(intel_scu_ipc_read_osnib_rr); - -/* - * This reads the PMIT from the OSHOB (pointer to interrupt tree) - */ -#ifdef DUMP_OSNIB -static int intel_scu_ipc_read_oshob_it_tree(u32 *ptr) -{ - return intel_scu_ipc_read_oshob((u8 *) ptr, 4, OSHOB_PMIT_OFFSET); -} -#endif - -/* - * This reads the RESETIRQ1 from the OSNIB - */ -#ifdef DUMP_OSNIB -static int intel_scu_ipc_read_osnib_resetirq1(u8 *rirq1) -{ - return intel_scu_ipc_read_oshob(rirq1, 1, OSNIB_RESETIRQ1_OFFSET); -} -#endif - -/* - * This reads the RESETIRQ2 from the OSNIB - */ -#ifdef DUMP_OSNIB -static int intel_scu_ipc_read_osnib_resetirq2(u8 *rirq2) -{ - return intel_scu_ipc_read_oshob(rirq2, 1, OSNIB_RESETIRQ2_OFFSET); -} -#endif - -static const struct file_operations scu_ipc_fops = { - .unlocked_ioctl = scu_ipc_ioctl, -}; - -static struct miscdevice scu_ipcutil = { - .minor = MISC_DYNAMIC_MINOR, - .name = "mid_ipc", - .fops = &scu_ipc_fops, -}; - -static int __init ipc_module_init(void) -{ -#ifdef DUMP_OSNIB - u8 rr, resetirq1, resetirq2, *ptr; - u32 pmit; -#endif - -#ifdef DUMP_OSNIB - /* Dumping RESETIRQ1 and 2 from the interrupt tree */ - intel_scu_ipc_read_oshob_it_tree(&pmit); - ptr = ioremap_nocache(pmit + PMIT_RESETIRQ1_OFFSET, 2); - if (ptr) { - resetirq1 = readb(ptr); - resetirq2 = readb(ptr+1); - pr_warn("[BOOT] RESETIRQ1=0x%02x RESETIRQ2=0x%02x " - "(interrupt tree)\n", - resetirq1, resetirq2); - iounmap(ptr); - } - - /* Dumping OSNIB content */ - intel_scu_ipc_read_osnib_rr(&rr); - intel_scu_ipc_read_osnib_resetirq1(&resetirq1); - intel_scu_ipc_read_osnib_resetirq2(&resetirq2); - pr_warn("[BOOT] RR=0x%02x (osnib)\n", rr); - pr_warn("[BOOT] RESETIRQ1=0x%02x RESETIRQ2=0x%02x " - "(osnib)\n", - resetirq1, resetirq2); -#endif - - return misc_register(&scu_ipcutil); -} - -static void __exit ipc_module_exit(void) -{ - misc_deregister(&scu_ipcutil); -} - -module_init(ipc_module_init); -module_exit(ipc_module_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("Utility driver for intel scu ipc"); -MODULE_AUTHOR("Sreedhara "); diff --git a/drivers/watchdog/intel_scu_watchdog.c b/drivers/watchdog/intel_scu_watchdog.c index 935379b..5820bf7 100644 --- a/drivers/watchdog/intel_scu_watchdog.c +++ b/drivers/watchdog/intel_scu_watchdog.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include "intel_scu_watchdog.h" @@ -399,7 +400,7 @@ int ret; /* Let shared OSNIB (sram) know we are open */ /* To publish a proc and ioctl to do this and leave userland decide */ /* when it is sensible to do it (boot completed intent) */ - ret = intel_scu_ipc_write_osnib(&osnib_reset, OSNIB_WRITE_SIZE, + ret = intel_mid_osip_write_osnib(&osnib_reset, OSNIB_WRITE_SIZE, OSNIB_WDOG_OFFSET, OSNIB_WRITE_MASK); if (ret != 0) { -- 2.7.4