From 6162fba57ca099d8fe9c609264b39e73323130a5 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 26 Jan 2019 16:40:03 +0000 Subject: [PATCH] [X86][SSE] Generalized unsigned compares to support nonsplat constant vectors (PR39859) llvm-svn: 352283 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 17 ++++++++++------- llvm/test/CodeGen/X86/sat-add.ll | 6 ++---- llvm/test/CodeGen/X86/vec_setcc-2.ll | 6 ++---- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1edcc02..a069b57 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -19604,17 +19604,20 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, TLI.isOperationLegal(ISD::UMIN, VT)) { // If we have a constant operand, increment/decrement it and change the // condition to avoid an invert. - // TODO: This could be extended to handle a non-splat constant by checking - // that each element of the constant is not the max/null value. - APInt C; - if (Cond == ISD::SETUGT && isConstantSplat(Op1, C) && !C.isMaxValue()) { + if (Cond == ISD::SETUGT && + ISD::matchUnaryPredicate(Op1, [](ConstantSDNode *C) { + return !C->getAPIntValue().isMaxValue(); + })) { // X > C --> X >= (C+1) --> X == umax(X, C+1) - Op1 = DAG.getConstant(C + 1, dl, VT); + Op1 = DAG.getNode(ISD::ADD, dl, VT, Op1, DAG.getConstant(1, dl, VT)); Cond = ISD::SETUGE; } - if (Cond == ISD::SETULT && isConstantSplat(Op1, C) && !C.isNullValue()) { + if (Cond == ISD::SETULT && + ISD::matchUnaryPredicate(Op1, [](ConstantSDNode *C) { + return !C->getAPIntValue().isNullValue(); + })) { // X < C --> X <= (C-1) --> X == umin(X, C-1) - Op1 = DAG.getConstant(C - 1, dl, VT); + Op1 = DAG.getNode(ISD::SUB, dl, VT, Op1, DAG.getConstant(1, dl, VT)); Cond = ISD::SETULE; } bool Invert = false; diff --git a/llvm/test/CodeGen/X86/sat-add.ll b/llvm/test/CodeGen/X86/sat-add.ll index e652f2c..78e4d5a 100644 --- a/llvm/test/CodeGen/X86/sat-add.ll +++ b/llvm/test/CodeGen/X86/sat-add.ll @@ -551,11 +551,9 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat(<4 x i32 ; SSE41: # %bb.0: ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [43,44,45,46] ; SSE41-NEXT: paddd %xmm0, %xmm1 -; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967252,4294967251,4294967250,4294967249] -; SSE41-NEXT: pminud %xmm0, %xmm2 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967253,4294967252,4294967251,4294967250] +; SSE41-NEXT: pmaxud %xmm0, %xmm2 ; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE41-NEXT: pxor %xmm2, %xmm0 ; SSE41-NEXT: por %xmm1, %xmm0 ; SSE41-NEXT: retq %a = add <4 x i32> %x, diff --git a/llvm/test/CodeGen/X86/vec_setcc-2.ll b/llvm/test/CodeGen/X86/vec_setcc-2.ll index 946c9fc..2a0a166 100644 --- a/llvm/test/CodeGen/X86/vec_setcc-2.ll +++ b/llvm/test/CodeGen/X86/vec_setcc-2.ll @@ -511,11 +511,9 @@ define <4 x i1> @ugt_v4i32_nonsplat(<4 x i32> %x) { ; ; SSE41-LABEL: ugt_v4i32_nonsplat: ; SSE41: ## %bb.0: -; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967253,4294967254,4294967255,4294967256] -; SSE41-NEXT: pminud %xmm0, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967254,4294967255,4294967256,4294967257] +; SSE41-NEXT: pmaxud %xmm0, %xmm1 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE41-NEXT: pxor %xmm1, %xmm0 ; SSE41-NEXT: retq %cmp = icmp ugt <4 x i32> %x, ret <4 x i1> %cmp -- 2.7.4