From 613f12dd8e2403f5630ab299d2a1bb2cb111ead1 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 23 Apr 2020 01:34:57 -0700 Subject: [PATCH] [AArch64][GlobalISel] Set the current debug loc when missing in some cases. --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 4 ++-- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 6 +++--- .../AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir | 1 + llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir | 1 + llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 2 +- 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 47c723c..09e303e 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -570,7 +570,7 @@ llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, } const char *Name = TLI.getLibcallName(RTLibcall); - MIRBuilder.setInstr(MI); + MIRBuilder.setInstrAndDebugLoc(MI); CallLowering::CallLoweringInfo Info; Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); @@ -3610,7 +3610,7 @@ LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, LegalizerHelper::LegalizeResult LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy) { - MIRBuilder.setInstr(MI); + MIRBuilder.setInstrAndDebugLoc(MI); unsigned Opc = MI.getOpcode(); switch (Opc) { case TargetOpcode::G_IMPLICIT_DEF: diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 60ccb36..cae5028 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -675,7 +675,7 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr( if (Amount > 31) return true; // This will have to remain a register variant. assert(MRI.getType(AmtReg).getSizeInBits() == 32); - MIRBuilder.setInstr(MI); + MIRBuilder.setInstrAndDebugLoc(MI); auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg); MI.getOperand(2).setReg(ExtCst.getReg(0)); return true; @@ -704,7 +704,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore( return false; } - MIRBuilder.setInstr(MI); + MIRBuilder.setInstrAndDebugLoc(MI); unsigned PtrSize = ValTy.getElementType().getSizeInBits(); const LLT NewTy = LLT::vector(ValTy.getNumElements(), PtrSize); auto &MMO = **MI.memoperands_begin(); @@ -722,7 +722,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore( bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const { - MIRBuilder.setInstr(MI); + MIRBuilder.setInstrAndDebugLoc(MI); MachineFunction &MF = MIRBuilder.getMF(); Align Alignment(MI.getOperand(2).getImm()); Register Dst = MI.getOperand(0).getReg(); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir index 6d50898..5b32fd51 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir index 7ccb516..dc42d60 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --- name: test_shift body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir index fe1d5a5..7446fde 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer --debugify-and-strip-all-safe --debugify-level=locations %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" -- 2.7.4