From 611db1c78fcbbe5de633101006dc5c4c087b72cb Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 20 Nov 2022 12:22:11 +0000 Subject: [PATCH] [X86] Remove unnecessary bit test instruction overrides from znver2 model Reported by D138359 and confirmed with AMD SoG - matches znver1 model --- llvm/lib/Target/X86/X86ScheduleZnver2.td | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td index 0428656..90b66d2 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver2.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td @@ -706,18 +706,7 @@ def Zn2WriteALULat2Ld : SchedWriteRes<[Zn2AGU, Zn2ALU]> { let Latency = 6; } -// BT. -// m,i. -def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>; - // BTR BTS BTC. -// r,r,i. -def Zn2WriteBTRSC : SchedWriteRes<[Zn2ALU]> { - let Latency = 2; - let NumMicroOps = 2; -} -def : InstRW<[Zn2WriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>; - // m,r,i. def Zn2WriteBTRSCm : SchedWriteRes<[Zn2AGU, Zn2ALU]> { let Latency = 6; -- 2.7.4