From 60f993ce170b91876ad41e8f7339c24afd63fac2 Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Mon, 15 Apr 2019 11:58:47 +0100 Subject: [PATCH] [binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das Andre Vieira * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns. --- bfd/ChangeLog | 6 ++ bfd/bfd-in2.h | 3 + bfd/libbfd.h | 1 + bfd/reloc.c | 5 ++ gas/ChangeLog | 22 ++++++ gas/config/tc-arm.c | 113 +++++++++++++++++++++++++++ gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d | 4 + gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l | 7 ++ gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s | 12 +++ gas/testsuite/gas/arm/armv8_1-m-loloop.d | 17 ++++ gas/testsuite/gas/arm/armv8_1-m-loloop.s | 14 ++++ opcodes/ChangeLog | 5 ++ opcodes/arm-dis.c | 37 +++++++++ 13 files changed, 246 insertions(+) create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop.s diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 0153964..7876f51 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,5 +1,11 @@ 2019-04-15 Sudakshina Das + * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. + * bfd-in2.h: Regenerated. + * libbfd.h: Regenerated. + +2019-04-15 Sudakshina Das + * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 4a3fa75..540b9f7 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -3579,6 +3579,9 @@ field in the instruction. */ /* ARM 19-bit pc-relative branch for Branch Future Link instruction. */ BFD_RELOC_ARM_THUMB_BF19, +/* ARM 12-bit pc-relative branch for Low Overhead Loop instructions. */ + BFD_RELOC_ARM_THUMB_LOOP12, + /* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. The lowest bit must be zero and is not stored in the instruction. Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 32080db..f64a8f3 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1534,6 +1534,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARM_THUMB_BF17", "BFD_RELOC_ARM_THUMB_BF13", "BFD_RELOC_ARM_THUMB_BF19", + "BFD_RELOC_ARM_THUMB_LOOP12", "BFD_RELOC_THUMB_PCREL_BRANCH7", "BFD_RELOC_THUMB_PCREL_BRANCH9", "BFD_RELOC_THUMB_PCREL_BRANCH12", diff --git a/bfd/reloc.c b/bfd/reloc.c index c0e413c..e6ba9e2 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -3040,6 +3040,11 @@ ENUMDOC ARM 19-bit pc-relative branch for Branch Future Link instruction. ENUM + BFD_RELOC_ARM_THUMB_LOOP12 +ENUMDOC + ARM 12-bit pc-relative branch for Low Overhead Loop instructions. + +ENUM BFD_RELOC_THUMB_PCREL_BRANCH7 ENUMX BFD_RELOC_THUMB_PCREL_BRANCH9 diff --git a/gas/ChangeLog b/gas/ChangeLog index fe9856a..ecb3702 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,6 +1,28 @@ 2019-04-15 Sudakshina Das Andre Vieira + * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR + for the LR operand and optional LR operand. + (parse_operands): Add switch cases for OP_LR and OP_oLR for + both type checking and value checking. + (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. + (v8_1_loop_reloc): New helper function for handling labels + for the low overhead loop instructions. + (do_t_loloop): New function to encode DLS, WLS and LE. + (insns): New entries for WLS, DLS and LE. + (md_pcrel_from_section): New switch case + for BFD_RELOC_ARM_THUMB_LOOP12. + (md_appdy_fix): Likewise. + (tc_gen_reloc): Likewise. + * testsuite/gas/arm/armv8_1-m-tloop.s: New. + * testsuite/gas/arm/armv8_1-m-tloop.d: New. + * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. + * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. + * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. + +2019-04-15 Sudakshina Das + Andre Vieira + * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 5e59078..828dfc1 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -6543,6 +6543,10 @@ enum operand_parse_code OP_RIWG, /* iWMMXt wCG register */ OP_RXA, /* XScale accumulator register */ + /* New operands for Armv8.1-M Mainline. */ + OP_LR, /* ARM LR register */ + OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */ + OP_REGLST, /* ARM register list */ OP_VRSLST, /* VFP single-precision register list */ OP_VRDLST, /* VFP double-precision register list */ @@ -6622,6 +6626,7 @@ enum operand_parse_code OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ OP_oRR, /* ARM register */ + OP_oLR, /* ARM LR register */ OP_oRRnpc, /* ARM register, not the PC */ OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ OP_oRRw, /* ARM register, not r15, optional trailing ! */ @@ -6790,6 +6795,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) case OP_RRnpc: case OP_RRnpcsp: case OP_oRR: + case OP_LR: + case OP_oLR: case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; @@ -7307,6 +7314,12 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) inst.operands[i].imm = val; break; + case OP_LR: + case OP_oLR: + if (inst.operands[i].reg != REG_LR) + inst.error = _("operand must be LR register"); + break; + default: break; } @@ -10518,6 +10531,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_cpsid, b670, f3af8600), \ X(_cpy, 4600, ea4f0000), \ X(_dec_sp,80dd, f1ad0d00), \ + X(_dls, 0000, f040e001), \ X(_eor, 4040, ea800000), \ X(_eors, 4040, ea900000), \ X(_inc_sp,00dd, f10d0d00), \ @@ -10530,6 +10544,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_ldr_pc,4800, f85f0000), \ X(_ldr_pc2,4800, f85f0000), \ X(_ldr_sp,9800, f85d0000), \ + X(_le, 0000, f00fc001), \ X(_lsl, 0000, fa00f000), \ X(_lsls, 0000, fa10f000), \ X(_lsr, 0800, fa20f000), \ @@ -10571,6 +10586,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_yield, bf10, f3af8001), \ X(_wfe, bf20, f3af8002), \ X(_wfi, bf30, f3af8003), \ + X(_wls, 0000, f040c001), \ X(_sev, bf40, f3af8004), \ X(_sevl, bf50, f3af8005), \ X(_udf, de00, f7f0a000) @@ -13434,6 +13450,64 @@ do_t_branch_future (void) } } +/* Helper function for do_t_loloop to handle relocations. */ +static void +v8_1_loop_reloc (int is_le) +{ + if (inst.relocs[0].exp.X_op == O_constant) + { + int value = inst.relocs[0].exp.X_add_number; + value = (is_le) ? -value : value; + + if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) + as_bad (BAD_BRANCH_OFF); + + int imml, immh; + + immh = (value & 0x00000ffc) >> 2; + imml = (value & 0x00000002) >> 1; + + inst.instruction |= (imml << 11) | (immh << 1); + } + else + { + inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12; + inst.relocs[0].pc_rel = 1; + } +} + +/* To handle the Scalar Low Overhead Loop instructions + in Armv8.1-M Mainline. */ +static void +do_t_loloop (void) +{ + unsigned long insn = inst.instruction; + + set_it_insn_type (OUTSIDE_IT_INSN); + inst.instruction = THUMB_OP32 (inst.instruction); + + switch (insn) + { + case T_MNEM_le: + /* le