From 60cdadace3208001b4e24a1a4b102f767d5df3c2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 20 Jul 2020 11:19:14 +1000 Subject: [PATCH] drm/nouveau/fence: use NVIDIA's headers for emit() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../gpu/drm/nouveau/include/nvhw/class/cl006e.h | 30 +++++++++++++++++ .../gpu/drm/nouveau/include/nvhw/class/cl826f.h | 39 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_dma.h | 5 --- drivers/gpu/drm/nouveau/nv10_fence.c | 4 ++- drivers/gpu/drm/nouveau/nv84_fence.c | 22 +++++++----- drivers/gpu/drm/nouveau/nvc0_fence.c | 21 ++++++++---- 6 files changed, 100 insertions(+), 21 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h new file mode 100644 index 0000000..8cfb596 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h @@ -0,0 +1,30 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ +#ifndef _cl006e_h_ +#define _cl006e_h_ + +/* fields and values */ +#define NV06E_SET_OBJECT (0x00000000) +#define NV06E_REFERENCE (0x00000048) +#define NV06E_SET_REFERENCE (0x00000050) +#endif /* _cl006e_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h new file mode 100644 index 0000000..8e7c0fb --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h @@ -0,0 +1,39 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ +#ifndef _cl826f_h_ +#define _cl826f_h_ + +#define NV826F_SEMAPHOREA (0x00000010) +#define NV826F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NV826F_SEMAPHOREB (0x00000014) +#define NV826F_SEMAPHOREB_OFFSET_LOWER 31:00 +#define NV826F_SEMAPHOREC (0x00000018) +#define NV826F_SEMAPHOREC_PAYLOAD 31:0 +#define NV826F_SEMAPHORED (0x0000001C) +#define NV826F_SEMAPHORED_OPERATION 2:0 +#define NV826F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NV826F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NV826F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NV826F_NON_STALLED_INTERRUPT (0x00000020) +#define NV826F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060) +#endif /* _cl826f_h_ */ diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 3f86cdf..ebe6339 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -104,7 +104,6 @@ WIND_RING(struct nouveau_channel *chan) } /* FIFO methods */ -#define NV01_SUBCHAN_OBJECT 0x00000000 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 @@ -113,14 +112,10 @@ WIND_RING(struct nouveau_channel *chan) #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 -#define NV84_SUBCHAN_UEVENT 0x00000020 -#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 -#define NV10_SUBCHAN_REF_CNT 0x00000050 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c -#define NV40_SUBCHAN_YIELD 0x00000080 /* NV_SW object class */ #define NV_SW_DMA_VBLSEM 0x0000018c diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c index b5117b0..8e3f034 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.c +++ b/drivers/gpu/drm/nouveau/nv10_fence.c @@ -27,13 +27,15 @@ #include +#include + int nv10_fence_emit(struct nouveau_fence *fence) { struct nvif_push *push = fence->channel->chan.push; int ret = PUSH_WAIT(push, 2); if (ret == 0) { - PUSH_NVSQ(push, NV06E, NV10_SUBCHAN_REF_CNT, fence->base.seqno); + PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno); PUSH_KICK(push); } return ret; diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index bc09e64..ec282f9 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -30,20 +30,26 @@ #include +#include + static int nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 8); if (ret == 0) { - PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle); - PUSH_NVSQ(push, NV826F, - NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, - NV84_SUBCHAN_SEMAPHORE_TRIGGER, - NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, - NV84_SUBCHAN_UEVENT, 0x00000000); + PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle); + + PUSH_MTHD(push, NV826F, SEMAPHOREA, + NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)), + + SEMAPHOREB, lower_32_bits(virtual), + SEMAPHOREC, sequence, + + SEMAPHORED, + NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE), + + NON_STALLED_INTERRUPT, 0); PUSH_KICK(push); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c index 13b1345..f46a890 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fence.c +++ b/drivers/gpu/drm/nouveau/nvc0_fence.c @@ -29,19 +29,26 @@ #include +#include + static int nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 6); if (ret == 0) { - PUSH_NVSQ(push, NV906F, - NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, - NV84_SUBCHAN_SEMAPHORE_TRIGGER, - NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, - NV84_SUBCHAN_UEVENT, 0x00000000); + PUSH_MTHD(push, NV906F, SEMAPHOREA, + NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)), + + SEMAPHOREB, lower_32_bits(virtual), + SEMAPHOREC, sequence, + + SEMAPHORED, + NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) | + NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, EN) | + NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE), + + NON_STALL_INTERRUPT, 0); PUSH_KICK(push); } return ret; -- 2.7.4