From 60bdfe5a7c712f240cba53b7f1803e78ad1edfef Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Mon, 31 Oct 2016 19:47:52 +0000 Subject: [PATCH] [PPC] add absolute difference altivec instructions and matching intrinsics This patch corresponds to review https://reviews.llvm.org/D26072. Committing on behalf of Sean Fertile. llvm-svn: 285627 --- llvm/include/llvm/IR/IntrinsicsPowerPC.td | 5 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 11 ++++++ llvm/test/CodeGen/PowerPC/vec_absd.ll | 40 ++++++++++++++++++++++ .../MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt | 9 +++++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s | 13 +++++++ 5 files changed, 78 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/vec_absd.ll diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 5dfd823..9edafdf 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -704,6 +704,11 @@ def int_ppc_altivec_crypto_vpmsumw : def int_ppc_altivec_crypto_vpmsumd : PowerPC_Vec_DDD_Intrinsic<"crypto_vpmsumd">; +// Absolute Difference intrinsics +def int_ppc_altivec_vabsdub : PowerPC_Vec_BBB_Intrinsic<"vabsdub">; +def int_ppc_altivec_vabsduh : PowerPC_Vec_HHH_Intrinsic<"vabsduh">; +def int_ppc_altivec_vabsduw : PowerPC_Vec_WWW_Intrinsic<"vabsduw">; + //===----------------------------------------------------------------------===// // PowerPC VSX Intrinsic Definitions. diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 83ebf28..2e01c8b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1412,4 +1412,15 @@ def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; // Decimal (Unsigned) Truncate def BCDTRUNCo : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; + +// Absolute Difference +def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "vabsdub $vD, $vA, $vB", IIC_VecGeneral, + [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; +def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "vabsduh $vD, $vA, $vB", IIC_VecGeneral, + [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; +def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "vabsduw $vD, $vA, $vB", IIC_VecGeneral, + [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; } // end HasP9Altivec diff --git a/llvm/test/CodeGen/PowerPC/vec_absd.ll b/llvm/test/CodeGen/PowerPC/vec_absd.ll new file mode 100644 index 0000000..37a3a5c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_absd.ll @@ -0,0 +1,40 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +; Check the vabsd* instructions that were added in PowerISA V3.0 + +; Function Attrs: nounwind readnone +declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>) + +; Function Attrs: nounwind readnone +declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>) + +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>) + +define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) { +entry: + %res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +; CHECK-LABEL: @test_byte +; CHECK: vabsdub 2, 2, 3 +; CHECK blr +} + +define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) { +entry: + %res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +; CHECK-LABEL: @test_half +; CHECK: vabsduh 2, 2, 3 +; CHECK blr +} + +define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) { +entry: + %res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +; CHECK-LABEL: @test_word +; CHECK: vabsduw 2, 2, 3 +; CHECK: blr +} diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt index b2b4976..cb43a7c 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -838,6 +838,15 @@ # CHECK: vmul10ecuq 2, 3, 4 0x10 0x43 0x20 0x41 +#CHECK: vabsdub 2, 3, 4 +0x10 0x43 0x24 0x03 + +#CHECK vabsduh 2, 3, 4 +0x10 0x43 0x24 0x43 + +#CHECK vabsduw 2, 3, 4 +0x10 0x43 0x24 0x83 + # CHECK: bcdcfn. 27, 31, 1 0x13 0x67 0xff 0x81 diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s index 7ac4ce9..16c48a7 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -933,6 +933,19 @@ # CHECK-LE: vmul10ecuq 2, 3, 4 # encoding: [0x41,0x20,0x43,0x10] vmul10ecuq 2, 3, 4 +# Vector Absolute Difference +# CHECK-BE: vabsdub 2, 3, 4 # encoding: [0x10,0x43,0x24,0x03] +# CHECK-LE: vabsdub 2, 3, 4 # encoding: [0x03,0x24,0x43,0x10] + vabsdub 2, 3, 4 + +# CHECK-BE: vabsduh 2, 3, 4 # encoding: [0x10,0x43,0x24,0x43] +# CHECK-LE: vabsduh 2, 3, 4 # encoding: [0x43,0x24,0x43,0x10] + vabsduh 2, 3, 4 + +# CHECK-BE: vabsduw 2, 3, 4 # encoding: [0x10,0x43,0x24,0x83] +# CHECK-LE: vabsduw 2, 3, 4 # encoding: [0x83,0x24,0x43,0x10] + vabsduw 2, 3, 4 + # Decimal Convert From/to National/Zoned/Signed-QWord # CHECK-BE: bcdcfn. 27, 31, 1 # encoding: [0x13,0x67,0xff,0x81] # CHECK-LE: bcdcfn. 27, 31, 1 # encoding: [0x81,0xff,0x67,0x13] -- 2.7.4