From 60a20e6879e4ce0911b12848ffd9e372f096590e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 23 Apr 2017 20:14:42 +0200 Subject: [PATCH] radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct register MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Cc: 17.1 Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++- src/gallium/drivers/radeonsi/si_state_shaders.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 9b7b52c..193187b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -379,7 +379,8 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen, S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) | - S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class >= VI ? + /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ + S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ? max_primgroup_in_wave : 0) | S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) | S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 21185c3..34cd6d4 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2542,6 +2542,9 @@ static void si_update_vgt_shader_config(struct si_context *sctx) S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); } + if (sctx->b.chip_class >= GFX9) + stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); + si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages); } si_pm4_bind_state(sctx, vgt_shader_config, *pm4); -- 2.7.4