From 6088f84398847152ad97eb1bc0b139a28e879b48 Mon Sep 17 00:00:00 2001
From: Yi-Hong Lyu <Yi-Hong.Lyu@ibm.com>
Date: Mon, 7 Oct 2019 05:29:11 +0000
Subject: [PATCH] [NFC][CGP] Tests for making ICMP_EQ use CR result of
 ICMP_S(L|G)T dominators

llvm-svn: 373876
---
 .../AArch64/use-cr-result-of-dom-icmp-st.ll        | 547 ++++++++++++++++++
 .../PowerPC/use-cr-result-of-dom-icmp-st.ll        | 492 ++++++++--------
 .../CodeGen/X86/use-cr-result-of-dom-icmp-st.ll    | 627 +++++++++++++++++++++
 3 files changed, 1434 insertions(+), 232 deletions(-)
 create mode 100644 llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
 create mode 100644 llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll

diff --git a/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll b/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
new file mode 100644
index 0000000..31cc59c
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
@@ -0,0 +1,547 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -verify-machineinstrs < %s | FileCheck %s
+
+; Test cases are generated from:
+; long long NAME(PARAM a, PARAM b) {
+;   if (LHS > RHS)
+;     return b;
+;   if (LHS < RHS)
+;     return a;\
+;   return a * b;
+; }
+; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
+; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
+
+target datalayout = "e-m:e-i64:64-n32:64"
+
+define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmn x8, #2 // =2
+; CHECK-NEXT:    b.le .LBB0_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    tbnz x8, #63, .LBB1_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB1_2: // %if.end
+; CHECK-NEXT:    cmn x8, #1 // =1
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmp x8, #0 // =0
+; CHECK-NEXT:    b.le .LBB2_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB2_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 0
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmp x8, #1 // =1
+; CHECK-NEXT:    b.le .LBB3_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB3_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmp x8, #2 // =2
+; CHECK-NEXT:    b.le .LBB4_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB4_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x0, #2 // =2
+; CHECK-NEXT:    b.le .LBB5_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB5_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    tbnz x0, #63, .LBB6_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB6_2: // %if.end
+; CHECK-NEXT:    cmn x0, #1 // =1
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp x0, #0 // =0
+; CHECK-NEXT:    b.le .LBB7_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB7_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 0
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp x0, #1 // =1
+; CHECK-NEXT:    b.le .LBB8_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB8_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp x0, #2 // =2
+; CHECK-NEXT:    b.le .LBB9_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB9_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmn w8, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmn w8, #1 // =1
+; CHECK-NEXT:    csinc w9, w1, wzr, eq
+; CHECK-NEXT:    mul w9, w9, w0
+; CHECK-NEXT:    cmp w8, #0 // =0
+; CHECK-NEXT:    csel w8, w1, w9, ge
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmp w8, #0 // =0
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 0
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmp w8, #1 // =1
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmp w8, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, #1 // =1
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    csel w8, w1, w8, ge
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 0
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, #1 // =1
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
diff --git a/llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll b/llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
index 7839669..3a41db0 100644
--- a/llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
+++ b/llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 < %s | FileCheck %s -check-prefix=PPC64LE
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s
 
 ; Test cases are generated from:
 ; long long NAME(PARAM a, PARAM b) {
@@ -13,22 +13,21 @@
 ; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
 
 target datalayout = "e-m:e-i64:64-n32:64"
-target triple = "powerpc64le-unknown-linux-gnu"
 
 define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, -2
-; PPC64LE-NEXT:    ble 0, .LBB0_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB0_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld r5, r3, r4
+; CHECK-NEXT:    cmpdi r5, -2
+; CHECK-NEXT:    ble cr0, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_2: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2
@@ -45,19 +44,19 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, -1
-; PPC64LE-NEXT:    ble 0, .LBB1_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB1_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld r5, r3, r4
+; CHECK-NEXT:    cmpdi r5, -1
+; CHECK-NEXT:    ble cr0, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB1_2: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -1
@@ -74,19 +73,19 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld. 5, 3, 4
-; PPC64LE-NEXT:    ble 0, .LBB2_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB2_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 5, 0
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld. r5, r3, r4
+; CHECK-NEXT:    ble cr0, .LBB2_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB2_2: # %if.end
+; CHECK-NEXT:    cmpldi r5, 0
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 0
@@ -103,20 +102,20 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, 1
-; PPC64LE-NEXT:    ble 0, .LBB3_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB3_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 5, 1
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld r5, r3, r4
+; CHECK-NEXT:    cmpdi r5, 1
+; CHECK-NEXT:    ble cr0, .LBB3_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB3_2: # %if.end
+; CHECK-NEXT:    cmpldi r5, 1
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
@@ -133,20 +132,20 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, 2
-; PPC64LE-NEXT:    ble 0, .LBB4_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB4_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 5, 2
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld r5, r3, r4
+; CHECK-NEXT:    cmpdi r5, 2
+; CHECK-NEXT:    ble cr0, .LBB4_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB4_2: # %if.end
+; CHECK-NEXT:    cmpldi r5, 2
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
@@ -163,18 +162,18 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a__2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, -2
-; PPC64LE-NEXT:    ble 0, .LBB5_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB5_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi r3, -2
+; CHECK-NEXT:    ble cr0, .LBB5_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB5_2: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end
@@ -190,18 +189,18 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a__1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, -1
-; PPC64LE-NEXT:    ble 0, .LBB6_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB6_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi r3, -1
+; CHECK-NEXT:    ble cr0, .LBB6_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB6_2: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   br i1 %cmp, label %return, label %if.end
@@ -217,19 +216,19 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a_0(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, 0
-; PPC64LE-NEXT:    ble 0, .LBB7_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB7_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 3, 0
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi r3, 0
+; CHECK-NEXT:    ble cr0, .LBB7_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB7_2: # %if.end
+; CHECK-NEXT:    cmpldi r3, 0
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   br i1 %cmp, label %return, label %if.end
@@ -245,19 +244,19 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a_1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, 1
-; PPC64LE-NEXT:    ble 0, .LBB8_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB8_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 3, 1
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi r3, 1
+; CHECK-NEXT:    ble cr0, .LBB8_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB8_2: # %if.end
+; CHECK-NEXT:    cmpldi r3, 1
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
@@ -273,19 +272,19 @@ return:                                           ; preds = %entry
 }
 
 define i64 @ll_a_2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, 2
-; PPC64LE-NEXT:    ble 0, .LBB9_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB9_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 3, 2
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi r3, 2
+; CHECK-NEXT:    ble cr0, .LBB9_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB9_2: # %if.end
+; CHECK-NEXT:    cmpldi r3, 2
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mulld r3, r4, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end
@@ -301,16 +300,18 @@ return:                                           ; preds = %entry
 }
 
 define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 6, -2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw r5, r3, r4
+; CHECK-NEXT:    cmpwi r5, -2
+; CHECK-NEXT:    bgt cr0, .LBB10_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:  .LBB10_2: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -2
@@ -329,16 +330,20 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 6, -1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw r5, r3, r4
+; CHECK-NEXT:    cmpwi r5, -1
+; CHECK-NEXT:    ble cr0, .LBB11_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB11_2: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -1
@@ -357,16 +362,21 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw. 5, 3, 4
-; PPC64LE-NEXT:    li 6, 1
-; PPC64LE-NEXT:    isel 6, 4, 6, 2
-; PPC64LE-NEXT:    cmpwi 5, 0
-; PPC64LE-NEXT:    mullw 3, 6, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw r5, r3, r4
+; CHECK-NEXT:    cmpwi r5, 0
+; CHECK-NEXT:    ble cr0, .LBB12_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB12_2: # %if.end
+; CHECK-NEXT:    cmplwi r5, 0
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 0
@@ -385,17 +395,19 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 6, 1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 6, 1
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw r5, r3, r4
+; CHECK-NEXT:    cmpwi r5, 1
+; CHECK-NEXT:    bgt cr0, .LBB13_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    cmplwi r5, 1
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:  .LBB13_2: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 1
@@ -414,17 +426,19 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 6, 2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 6, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw r5, r3, r4
+; CHECK-NEXT:    cmpwi r5, 2
+; CHECK-NEXT:    bgt cr0, .LBB14_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    cmplwi r5, 2
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:  .LBB14_2: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 2
@@ -443,15 +457,17 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a__2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 3, -2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpwi r3, -2
+; CHECK-NEXT:    bgt cr0, .LBB15_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:  .LBB15_2: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -2
   br i1 %cmp, label %return, label %if.end
@@ -469,15 +485,19 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a__1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 3, -1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpwi r3, -1
+; CHECK-NEXT:    ble cr0, .LBB16_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB16_2: # %if.end
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -1
   br i1 %cmp, label %return, label %if.end
@@ -495,16 +515,20 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a_0(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 3, 0
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 0, 3, 0
-; PPC64LE-NEXT:    mullw 5, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 5, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpwi r3, 0
+; CHECK-NEXT:    ble cr0, .LBB17_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB17_2: # %if.end
+; CHECK-NEXT:    cmplwi r3, 0
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %return, label %if.end
@@ -522,16 +546,18 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a_1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 3, 1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 0, 3, 1
-; PPC64LE-NEXT:    mullw 5, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 5, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpwi r3, 1
+; CHECK-NEXT:    bgt cr0, .LBB18_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    cmplwi r3, 1
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:  .LBB18_2: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 1
   br i1 %cmp, label %return, label %if.end
@@ -549,16 +575,18 @@ return:                                           ; preds = %if.end, %entry
 }
 
 define i64 @i_a_2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 3, 2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 0, 3, 2
-; PPC64LE-NEXT:    mullw 5, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 5, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpwi r3, 2
+; CHECK-NEXT:    bgt cr0, .LBB19_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    cmplwi r3, 2
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    mullw r4, r4, r3
+; CHECK-NEXT:  .LBB19_2: # %return
+; CHECK-NEXT:    extsw r3, r4
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 2
   br i1 %cmp, label %return, label %if.end
diff --git a/llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll b/llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll
new file mode 100644
index 0000000..adb9eb2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll
@@ -0,0 +1,627 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-unknown -O3 -verify-machineinstrs < %s | FileCheck %s
+
+; Test cases are generated from:
+; long long NAME(PARAM a, PARAM b) {
+;   if (LHS > RHS)
+;     return b;
+;   if (LHS < RHS)
+;     return a;\
+;   return a * b;
+; }
+; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
+; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
+
+target datalayout = "e-m:e-i64:64-n32:64"
+
+define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rcx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shlq %cl, %rax
+; CHECK-NEXT:    cmpq $-2, %rax
+; CHECK-NEXT:    jle .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB0_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rcx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shlq %cl, %rax
+; CHECK-NEXT:    testq %rax, %rax
+; CHECK-NEXT:    js .LBB1_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB1_1: # %if.end
+; CHECK-NEXT:    cmpq $-1, %rax
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rcx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shlq %cl, %rax
+; CHECK-NEXT:    testq %rax, %rax
+; CHECK-NEXT:    jle .LBB2_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB2_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 0
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rcx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shlq %cl, %rax
+; CHECK-NEXT:    cmpq $1, %rax
+; CHECK-NEXT:    jle .LBB3_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB3_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rcx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shlq %cl, %rax
+; CHECK-NEXT:    cmpq $2, %rax
+; CHECK-NEXT:    jle .LBB4_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB4_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpq $-2, %rdi
+; CHECK-NEXT:    jle .LBB5_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB5_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testq %rdi, %rdi
+; CHECK-NEXT:    js .LBB6_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB6_1: # %if.end
+; CHECK-NEXT:    cmpq $-1, %rdi
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testq %rdi, %rdi
+; CHECK-NEXT:    jle .LBB7_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB7_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 0
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpq $1, %rdi
+; CHECK-NEXT:    jle .LBB8_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB8_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpq $2, %rdi
+; CHECK-NEXT:    jle .LBB9_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB9_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    cmpl $-2, %eax
+; CHECK-NEXT:    jg .LBB10_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %ecx, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:  .LBB10_2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    js .LBB11_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB11_1: # %if.end
+; CHECK-NEXT:    cmpl $-1, %eax
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %ecx, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    jle .LBB12_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB12_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %ecx, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 0
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    cmpl $1, %eax
+; CHECK-NEXT:    jg .LBB13_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %ecx, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:  .LBB13_2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    cmpl $2, %eax
+; CHECK-NEXT:    jg .LBB14_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %ecx, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:  .LBB14_2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $-2, %edi
+; CHECK-NEXT:    jg .LBB15_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %esi, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:  .LBB15_2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    js .LBB16_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB16_1: # %if.end
+; CHECK-NEXT:    cmpl $-1, %edi
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %esi, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    jle .LBB17_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB17_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %esi, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 0
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $1, %edi
+; CHECK-NEXT:    jg .LBB18_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %esi, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:  .LBB18_2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $2, %edi
+; CHECK-NEXT:    jg .LBB19_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovel %esi, %eax
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:  .LBB19_2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
-- 
2.7.4