From 604c0ee37c031a902f28a3a181e1314c8bab46f3 Mon Sep 17 00:00:00 2001 From: Zhigang Gong Date: Tue, 27 May 2014 16:58:28 +0800 Subject: [PATCH] GBE: fix baytrail L3 cache configuration. Reduce URB from 128KB to 64KB causes rendering artifact in X window. I have to change it to 96KB URB and also change the RO and DC to 16KB to satisfy the total 192KB L3 size limitation. With this fix, the artifact is gone and utests has no new failures. Signed-off-by: Zhigang Gong Reviewed-by: Guo Yejun --- src/intel/intel_gpgpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index 9c773bd..fba480c 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -394,7 +394,7 @@ intel_gpgpu_set_L3_baytrail(intel_gpgpu_t *gpgpu, uint32_t use_slm) OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ OUT_BATCH(gpgpu->batch, GEN7_L3_CNTL_REG2_ADDRESS_OFFSET); if (use_slm) - OUT_BATCH(gpgpu->batch, 0x02040001); /* {SLM=64, URB=64, DC=32, RO=32, Sum=192} */ + OUT_BATCH(gpgpu->batch, 0x01020021); /* {SLM=64, URB=96, DC=16, RO=16, Sum=192} */ else OUT_BATCH(gpgpu->batch, 0x02040040); /* {SLM=0, URB=128, DC=32, RO=32, Sum=192} */ -- 2.7.4