From 604ba08ab4b3672b8d96f78a781937ad9e43971c Mon Sep 17 00:00:00 2001 From: Jonathan Wakely Date: Sat, 8 Jun 2019 14:40:25 +0100 Subject: [PATCH] Use consistent spelling of PCLMUL instruction * doc/invoke.texi (C Dialect Options): Minor grammatical change. (x86 Options): Replace all uses of "PCL_MUL" with "PCLMUL" From-SVN: r272081 --- gcc/ChangeLog | 5 +++++ gcc/doc/invoke.texi | 16 ++++++++-------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3721c87..5a6d6f6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-06-08 Jonathan Wakely + + * doc/invoke.texi (C Dialect Options): Minor grammatical change. + (x86 Options): Replace all uses of "PCL_MUL" with "PCLMUL" + 2019-06-07 John David Anglin PR target/90751 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index fa7d9ea..f18d225 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -2238,7 +2238,7 @@ Some cases of unnamed fields in structures and unions are only accepted with this option. @xref{Unnamed Fields,,Unnamed struct/union fields within structs/unions}, for details. -Note that this option is off for all targets but x86 +Note that this option is off for all targets except for x86 targets using ms-abi. @item -fplan9-extensions @@ -27376,34 +27376,34 @@ instruction set extensions.) @item bdver1 CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This -supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, +supersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) @item bdver2 AMD Family 15h core based CPUs with x86-64 instruction set support. (This -supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, +supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) @item bdver3 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES, -PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and +PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions. @item bdver4 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, -AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, +AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions. @item znver1 AMD Family 17h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, -SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, +SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit instruction set extensions. @item znver2 AMD Family 17h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, -MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, +MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit instruction set extensions.) @@ -27415,7 +27415,7 @@ instruction set extensions.) @item btver2 CPUs based on AMD Family 16h cores with x86-64 instruction set support. This -includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, +includes MOVBE, F16C, BMI, AVX, PCLMUL, AES, SSE4.2, SSE4.1, CX16, ABM, SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions. @item winchip-c6 -- 2.7.4