From 603c6455d2ffbff096acb5f2902e3212885ef379 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 7 Nov 2017 10:43:56 +0000 Subject: [PATCH] [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39087 llvm-svn: 317564 --- llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp index f6be8da..3b400c1 100644 --- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -603,6 +603,11 @@ bool TypeInfer::EnforceVectorSubVectorTypeIs(TypeSetByHwMode &Vec, auto IsSubVec = [](MVT B, MVT P) -> bool { if (!B.isVector() || !P.isVector()) return false; + // Logically a <4 x i32> is a valid subvector of + // but until there are obvious use-cases for this, keep the + // types separate. + if (B.isScalableVector() != P.isScalableVector()) + return false; if (B.getVectorElementType() != P.getVectorElementType()) return false; return B.getVectorNumElements() < P.getVectorNumElements(); -- 2.7.4