From 6011627f5118dd64a0c33694b604c70e766d8c40 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 7 Apr 2020 17:28:53 -0400 Subject: [PATCH] CodeGen: More conversions to use Register --- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 51 ++++++++++--------- llvm/lib/CodeGen/TargetRegisterInfo.cpp | 28 +++++------ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +-- llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 6 +-- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 +-- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 10 ++-- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 20 ++++---- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 26 +++++----- llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 65 ++++++++++++------------- llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 23 ++++----- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 10 ++-- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 2 +- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 55 +++++++++------------ llvm/lib/Target/ARM/MVEVPTBlockPass.cpp | 4 +- llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp | 6 +-- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 18 +++---- llvm/lib/Target/ARM/Thumb2InstrInfo.h | 6 +-- llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 8 +-- llvm/lib/Target/ARM/ThumbRegisterInfo.cpp | 23 +++++---- llvm/lib/Target/ARM/ThumbRegisterInfo.h | 8 +-- llvm/lib/Target/Mips/Mips16RegisterInfo.cpp | 12 ++--- llvm/lib/Target/Mips/Mips16RegisterInfo.h | 8 +-- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 22 ++++----- llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 10 ++-- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 2 +- llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp | 17 +++---- llvm/lib/Target/SystemZ/SystemZRegisterInfo.h | 6 +-- llvm/lib/Target/X86/X86RegisterInfo.cpp | 2 +- llvm/lib/Target/X86/X86RegisterInfo.h | 2 +- 30 files changed, 222 insertions(+), 244 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index ffbcb2b..31704f80 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -81,7 +81,7 @@ public: } /// Return the specified register in the class. - unsigned getRegister(unsigned i) const { + MCRegister getRegister(unsigned i) const { return MC->getRegister(i); } @@ -315,8 +315,8 @@ public: /// Returns the Register Class of a physical register of the given type, /// picking the most sub register class of the right type that contains this /// physreg. - const TargetRegisterClass * - getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const; + const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg, + MVT VT = MVT::Other) const; /// Return the maximal subclass of the given register class that is /// allocatable or NULL. @@ -331,12 +331,12 @@ public: /// Return the additional cost of using this register instead /// of other registers in its class. - unsigned getCostPerUse(unsigned RegNo) const { + unsigned getCostPerUse(MCRegister RegNo) const { return InfoDesc[RegNo].CostPerUse; } /// Return true if the register is in the allocation of any register class. - bool isInAllocatableClass(unsigned RegNo) const { + bool isInAllocatableClass(MCRegister RegNo) const { return InfoDesc[RegNo].inAllocatableClass; } @@ -520,8 +520,8 @@ public: /// Return a super-register of the specified register /// Reg so its sub-register of index SubIdx is Reg. - unsigned getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, - const TargetRegisterClass *RC) const { + MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, + const TargetRegisterClass *RC) const { return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); } @@ -605,8 +605,8 @@ public: } /// Debugging helper: dump register in human readable form to dbgs() stream. - static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0, - const TargetRegisterInfo* TRI = nullptr); + static void dumpReg(Register Reg, unsigned SubRegIndex = 0, + const TargetRegisterInfo *TRI = nullptr); protected: /// Overridden by TableGen in targets that have sub-registers. @@ -745,7 +745,7 @@ public: const TargetRegisterClass *RC) const = 0; /// Returns size in bits of a phys/virtual/generic register. - unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const; + unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const; /// Get the weight in units of pressure for this register unit. virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0; @@ -784,20 +784,19 @@ public: /// independent register allocation hints. Targets that override this /// function should typically call this default implementation as well and /// expect to see generic copy hints added. - virtual bool getRegAllocationHints(unsigned VirtReg, - ArrayRef Order, - SmallVectorImpl &Hints, - const MachineFunction &MF, - const VirtRegMap *VRM = nullptr, - const LiveRegMatrix *Matrix = nullptr) - const; + virtual bool + getRegAllocationHints(Register VirtReg, ArrayRef Order, + SmallVectorImpl &Hints, + const MachineFunction &MF, + const VirtRegMap *VRM = nullptr, + const LiveRegMatrix *Matrix = nullptr) const; /// A callback to allow target a chance to update register allocation hints /// when a register is "changed" (e.g. coalesced) to another register. /// e.g. On ARM, some virtual registers should target register pairs, /// if one of pair is coalesced to another register, the allocation hint of /// the other half of the pair should be changed to point to the new register. - virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, + virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const { // Do nothing. } @@ -855,7 +854,7 @@ public: /// spill slot. This tells PEI not to create a new stack frame /// object for the given register. It should be called only after /// determineCalleeSaves(). - virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, + virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const { return false; } @@ -892,7 +891,7 @@ public: /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx /// before insertion point I. virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, int FrameIdx, + Register BaseReg, int FrameIdx, int64_t Offset) const { llvm_unreachable("materializeFrameBaseRegister does not exist on this " "target"); @@ -900,14 +899,14 @@ public: /// Resolve a frame index operand of an instruction /// to reference the indicated base register plus offset instead. - virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const { llvm_unreachable("resolveFrameIndex does not exist on this target"); } /// Determine whether a given base register plus offset immediate is /// encodable to resolve a frame index. - virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, + virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const { llvm_unreachable("isFrameOffsetLegal does not exist on this target"); } @@ -920,7 +919,7 @@ public: MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, - unsigned Reg) const { + Register Reg) const { return false; } @@ -936,7 +935,7 @@ public: RegScavenger *RS = nullptr) const = 0; /// Return the assembly name for \p Reg. - virtual StringRef getRegAsmName(unsigned Reg) const { + virtual StringRef getRegAsmName(MCRegister Reg) const { // FIXME: We are assuming that the assembly name is equal to the TableGen // name converted to lower case // @@ -973,7 +972,7 @@ public: virtual Register getFrameRegister(const MachineFunction &MF) const = 0; /// Mark a register and all its aliases as reserved in the given set. - void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const; + void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const; /// Returns true if for every register in the set all super registers are part /// of the set as well. @@ -1177,7 +1176,7 @@ Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI); /// Create Printable object to print register classes or register banks /// on a \ref raw_ostream. -Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, +Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI); } // end namespace llvm diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index 5c6963e..e2ef12d 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -75,8 +75,8 @@ bool TargetRegisterInfo::shouldRegionSplitForVirtReg( return true; } -void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg) - const { +void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, + MCRegister Reg) const { for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI) RegisterSet.set(*AI); } @@ -170,7 +170,7 @@ Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { }); } -Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, +Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) { return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { if (RegInfo.getRegClassOrNull(Reg)) @@ -207,7 +207,7 @@ TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { /// register of the given type, picking the most sub register class of /// the right type that contains this physreg. const TargetRegisterClass * -TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { +TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const { assert(Register::isPhysicalRegister(reg) && "reg must be a physical register"); @@ -399,13 +399,10 @@ bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, } // Compute target-independent register allocator hints to help eliminate copies. -bool -TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, - ArrayRef Order, - SmallVectorImpl &Hints, - const MachineFunction &MF, - const VirtRegMap *VRM, - const LiveRegMatrix *Matrix) const { +bool TargetRegisterInfo::getRegAllocationHints( + Register VirtReg, ArrayRef Order, + SmallVectorImpl &Hints, const MachineFunction &MF, + const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const { const MachineRegisterInfo &MRI = MF.getRegInfo(); const std::pair> &Hints_MRI = MRI.getRegAllocationHints(VirtReg); @@ -489,10 +486,11 @@ bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, return true; } -unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg, - const MachineRegisterInfo &MRI) const { +unsigned +TargetRegisterInfo::getRegSizeInBits(Register Reg, + const MachineRegisterInfo &MRI) const { const TargetRegisterClass *RC{}; - if (Register::isPhysicalRegister(Reg)) { + if (Reg.isPhysical()) { // The size is not directly available for physical registers. // Instead, we need to access a register class that contains Reg and // get the size of that register class. @@ -536,7 +534,7 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg, #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD -void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, +void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex, const TargetRegisterInfo *TRI) { dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; } diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 282fe6a..c8556c2 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -399,7 +399,7 @@ bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, } bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, - unsigned BaseReg, + Register BaseReg, int64_t Offset) const { assert(MI && "Unable to get the legal offset for nil instruction."); StackOffset SaveOffset(Offset, MVT::i8); @@ -409,7 +409,7 @@ bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx /// at the beginning of the basic block. void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, + Register BaseReg, int FrameIdx, int64_t Offset) const { MachineBasicBlock::iterator Ins = MBB->begin(); @@ -430,7 +430,7 @@ void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, .addImm(Shifter); } -void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, +void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const { // ARM doesn't need the general 64-bit offsets StackOffset Off(Offset, MVT::i8); diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h index 4d28ce7..8c6bc53 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h @@ -96,12 +96,12 @@ public: bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; - bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, + bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, + void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, int FrameIdx, int64_t Offset) const override; - void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index deb1270..58ea6bc 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -386,7 +386,7 @@ bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { } void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, + Register BaseReg, int FrameIdx, int64_t Offset) const { MachineBasicBlock::iterator Ins = MBB->begin(); @@ -420,7 +420,7 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, .addImm(0); // clamp bit } -void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, +void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const { const SIInstrInfo *TII = ST.getInstrInfo(); @@ -457,7 +457,7 @@ void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, } bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, - unsigned BaseReg, + Register BaseReg, int64_t Offset) const { if (!SIInstrInfo::isMUBUF(*MI)) return false; @@ -1270,7 +1270,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, } } -StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const { +StringRef SIRegisterInfo::getRegAsmName(MCRegister Reg) const { return AMDGPUInstPrinter::getRegisterName(Reg); } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 8e50c26..308db1b 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -81,14 +81,14 @@ public: bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, int FrameIdx, + void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, + int FrameIdx, int64_t Offset) const override; - void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; - bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, + bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override; const TargetRegisterClass *getPointerRegClass( @@ -110,7 +110,7 @@ public: bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const; - StringRef getRegAsmName(unsigned Reg) const override; + StringRef getRegAsmName(MCRegister Reg) const override; unsigned getHWRegIndex(MCRegister Reg) const { return getEncodingValue(Reg) & 0xff; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index c17dfd0..fc4e718 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -829,7 +829,7 @@ void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) { } void llvm::addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, - unsigned DestReg) { + Register DestReg) { addUnpredicatedMveVpredNOp(MIB); MIB.addReg(DestReg, RegState::Undef); } @@ -2168,7 +2168,7 @@ ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, /// condition, otherwise returns AL. It also returns the condition code /// register by reference. ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI, - unsigned &PredReg) { + Register &PredReg) { int PIdx = MI.findFirstPredOperandIdx(); if (PIdx == -1) { PredReg = 0; @@ -2198,7 +2198,7 @@ MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI, case ARM::MOVCCr: case ARM::t2MOVCCr: { // MOVCC can be commuted by inverting the condition. - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); // MOVCC AL can't be inverted. Shouldn't happen. if (CC == ARMCC::AL || PredReg != ARM::CPSR) @@ -2219,9 +2219,9 @@ MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI, /// Identify instructions that can be folded into a MOVCC instruction, and /// return the defining instruction. MachineInstr * -ARMBaseInstrInfo::canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, +ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII) const { - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) return nullptr; if (!MRI.hasOneNonDBGUse(Reg)) return nullptr; @@ -2401,9 +2401,9 @@ unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, - unsigned BaseReg, int NumBytes, - ARMCC::CondCodes Pred, unsigned PredReg, + const DebugLoc &dl, Register DestReg, + Register BaseReg, int NumBytes, + ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) { if (NumBytes == 0 && DestReg != BaseReg) { @@ -2563,7 +2563,7 @@ bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, } bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, - unsigned FrameReg, int &Offset, + Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII) { unsigned Opcode = MI.getOpcode(); const MCInstrDesc &Desc = MI.getDesc(); @@ -5452,7 +5452,7 @@ MachineInstr *llvm::findCMPToFoldIntoCBZ(MachineInstr *Br, if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri) return nullptr; Register Reg = CmpMI->getOperand(0).getReg(); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*CmpMI, PredReg); if (Pred != ARMCC::AL || CmpMI->getOperand(1).getImm() != 0) return nullptr; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index fc3c579..9f23483 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -413,7 +413,7 @@ private: /// Identify instructions that can be folded into a MOVCC instruction, and /// return the defining instruction. - MachineInstr *canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, + MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII) const; private: @@ -701,7 +701,7 @@ static inline bool isValidCoprocessorNumber(unsigned Num, /// getInstrPredicate - If instruction is predicated, returns its predicate /// condition, otherwise returns AL. It also returns the condition code /// register by reference. -ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg); +ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg); unsigned getMatchingCondBranchOpcode(unsigned Opc); @@ -715,21 +715,21 @@ unsigned convertAddSubFlagsOpcode(unsigned OldOpc); /// code. void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, - unsigned BaseReg, int NumBytes, - ARMCC::CondCodes Pred, unsigned PredReg, + const DebugLoc &dl, Register DestReg, + Register BaseReg, int NumBytes, + ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, - unsigned BaseReg, int NumBytes, - ARMCC::CondCodes Pred, unsigned PredReg, + const DebugLoc &dl, Register DestReg, + Register BaseReg, int NumBytes, + ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, - unsigned BaseReg, int NumBytes, + const DebugLoc &dl, Register DestReg, + Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags = 0); @@ -748,11 +748,11 @@ bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, /// offset could not be handled directly in MI, and return the left-over /// portion by reference. bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, - unsigned FrameReg, int &Offset, + Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII); bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, - unsigned FrameReg, int &Offset, + Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI); @@ -767,7 +767,7 @@ MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI); void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB); -void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned DestReg); +void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg); void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond); void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index fac0ac4..d58bef6 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -289,7 +289,8 @@ ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, } // Get the other register in a GPRPair. -static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { +static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd, + const MCRegisterInfo *RI) { for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) if (ARM::GPRPairRegClass.contains(*Supers)) return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); @@ -297,15 +298,12 @@ static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { } // Resolve the RegPairEven / RegPairOdd register allocator hints. -bool -ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, - ArrayRef Order, - SmallVectorImpl &Hints, - const MachineFunction &MF, - const VirtRegMap *VRM, - const LiveRegMatrix *Matrix) const { +bool ARMBaseRegisterInfo::getRegAllocationHints( + Register VirtReg, ArrayRef Order, + SmallVectorImpl &Hints, const MachineFunction &MF, + const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const { const MachineRegisterInfo &MRI = MF.getRegInfo(); - std::pair Hint = MRI.getRegAllocationHint(VirtReg); + std::pair Hint = MRI.getRegAllocationHint(VirtReg); unsigned Odd; switch (Hint.first) { @@ -323,12 +321,12 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, // This register should preferably be even (Odd == 0) or odd (Odd == 1). // Check if the other part of the pair has already been assigned, and provide // the paired register as the first hint. - unsigned Paired = Hint.second; - if (Paired == 0) + Register Paired = Hint.second; + if (!Paired) return false; - unsigned PairedPhys = 0; - if (Register::isPhysicalRegister(Paired)) { + Register PairedPhys; + if (Paired.isPhysical()) { PairedPhys = Paired; } else if (VRM && VRM->hasPhys(Paired)) { PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this); @@ -339,11 +337,11 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, Hints.push_back(PairedPhys); // Then prefer even or odd registers. - for (unsigned Reg : Order) { + for (MCPhysReg Reg : Order) { if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) continue; // Don't provide hints that are paired to a reserved register. - unsigned Paired = getPairedGPR(Reg, !Odd, this); + MCPhysReg Paired = getPairedGPR(Reg, !Odd, this); if (!Paired || MRI.isReserved(Paired)) continue; Hints.push_back(Reg); @@ -351,27 +349,27 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, return false; } -void -ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, - MachineFunction &MF) const { +void ARMBaseRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg, + MachineFunction &MF) const { MachineRegisterInfo *MRI = &MF.getRegInfo(); - std::pair Hint = MRI->getRegAllocationHint(Reg); - if ((Hint.first == (unsigned)ARMRI::RegPairOdd || - Hint.first == (unsigned)ARMRI::RegPairEven) && - Register::isVirtualRegister(Hint.second)) { + std::pair Hint = MRI->getRegAllocationHint(Reg); + if ((Hint.first == ARMRI::RegPairOdd || Hint.first == ARMRI::RegPairEven) && + Hint.second.isVirtual()) { // If 'Reg' is one of the even / odd register pair and it's now changed // (e.g. coalesced) into a different register. The other register of the // pair allocation hint must be updated to reflect the relationship // change. - unsigned OtherReg = Hint.second; + Register OtherReg = Hint.second; Hint = MRI->getRegAllocationHint(OtherReg); // Make sure the pair has not already divorced. if (Hint.second == Reg) { MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); if (Register::isVirtualRegister(NewReg)) MRI->setRegAllocationHint(NewReg, - Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven - : ARMRI::RegPairOdd, OtherReg); + Hint.first == ARMRI::RegPairOdd + ? ARMRI::RegPairEven + : ARMRI::RegPairOdd, + OtherReg); } } } @@ -457,8 +455,8 @@ ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { /// specified immediate. void ARMBaseRegisterInfo::emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, - ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { + const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, + ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { MachineFunction &MF = *MBB.getParent(); const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineConstantPool *ConstantPool = MF.getConstantPool(); @@ -621,10 +619,10 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to /// be a pointer to FrameIdx at the beginning of the basic block. -void ARMBaseRegisterInfo:: -materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, int FrameIdx, - int64_t Offset) const { +void ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, + Register BaseReg, + int FrameIdx, + int64_t Offset) const { ARMFunctionInfo *AFI = MBB->getParent()->getInfo(); unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); @@ -647,7 +645,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB, MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); } -void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, +void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const { MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); @@ -675,7 +673,8 @@ void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, (void)Done; } -bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, +bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, + Register BaseReg, int64_t Offset) const { const MCInstrDesc &Desc = MI->getDesc(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h index f9f5057..7dc87da 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -149,14 +149,12 @@ public: unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override; - bool getRegAllocationHints(unsigned VirtReg, - ArrayRef Order, + bool getRegAllocationHints(Register VirtReg, ArrayRef Order, SmallVectorImpl &Hints, - const MachineFunction &MF, - const VirtRegMap *VRM, + const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override; - void updateRegAllocHint(unsigned Reg, unsigned NewReg, + void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const override; bool hasBasePointer(const MachineFunction &MF) const; @@ -165,28 +163,27 @@ public: int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override; bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, int FrameIdx, + void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, + int FrameIdx, int64_t Offset) const override; - void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; - bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, + bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override; bool cannotEliminateFrame(const MachineFunction &MF) const; // Debug information queries. Register getFrameRegister(const MachineFunction &MF) const override; - unsigned getBaseRegister() const { return BasePtr; } - + Register getBaseRegister() const { return BasePtr; } /// emitLoadConstPool - Emits a load from constpool to materialize the /// specified immediate. virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, + const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred = ARMCC::AL, - unsigned PredReg = 0, + Register PredReg = Register(), unsigned MIFlags = MachineInstr::NoFlags) const; /// Code Generation virtual methods... diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index f36468d..7254bdd 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -1353,8 +1353,8 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, // displacement. MachineBasicBlock::iterator I = UserMI; ++I; - for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI), - PredReg = 0; + Register PredReg; + for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI); I->getOpcode() != ARM::t2IT && getITInstrPredicate(*I, PredReg) != ARMCC::AL; Offset += TII->getInstSizeInBytes(*I), I = std::next(I)) { @@ -1399,7 +1399,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, // Avoid splitting an IT block. if (LastIT) { - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); if (CC != ARMCC::AL) MI = LastIT; @@ -1423,7 +1423,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, // We really must not split an IT block. #ifndef NDEBUG - unsigned PredReg; + Register PredReg; assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL); #endif NewMBB = splitBlockBeforeInstr(&*MI); @@ -1828,7 +1828,7 @@ bool ARMConstantIslands::optimizeThumb2Branches() { if (!Br.MI->killsRegister(ARM::CPSR)) return false; - unsigned PredReg = 0; + Register PredReg; unsigned NewOpc = 0; ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg); if (Pred == ARMCC::EQ) diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 4afa3a4..9e461c3 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -827,7 +827,7 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) { MachineInstr &MI = *MBBI; unsigned Opcode = MI.getOpcode(); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 381425f..852e3d7 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -900,7 +900,7 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) { unsigned Offset = getMemoryOpOffset(*First); Register Base = getLoadStoreBaseOp(*First).getReg(); bool BaseKill = LatestMI->killsRegister(Base); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); DebugLoc DL = First->getDebugLoc(); MachineInstr *Merged = nullptr; @@ -1183,8 +1183,8 @@ static unsigned getUpdatingLSMultipleOpcode(unsigned Opc, /// Check if the given instruction increments or decrements a register and /// return the amount it is incremented/decremented. Returns 0 if the CPSR flags /// generated by the instruction are possibly read as well. -static int isIncrementOrDecrement(const MachineInstr &MI, unsigned Reg, - ARMCC::CondCodes Pred, unsigned PredReg) { +static int isIncrementOrDecrement(const MachineInstr &MI, Register Reg, + ARMCC::CondCodes Pred, Register PredReg) { bool CheckCPSRDef; int Scale; switch (MI.getOpcode()) { @@ -1201,7 +1201,7 @@ static int isIncrementOrDecrement(const MachineInstr &MI, unsigned Reg, default: return 0; } - unsigned MIPredReg; + Register MIPredReg; if (MI.getOperand(0).getReg() != Reg || MI.getOperand(1).getReg() != Reg || getInstrPredicate(MI, MIPredReg) != Pred || @@ -1215,8 +1215,8 @@ static int isIncrementOrDecrement(const MachineInstr &MI, unsigned Reg, /// Searches for an increment or decrement of \p Reg before \p MBBI. static MachineBasicBlock::iterator -findIncDecBefore(MachineBasicBlock::iterator MBBI, unsigned Reg, - ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { +findIncDecBefore(MachineBasicBlock::iterator MBBI, Register Reg, + ARMCC::CondCodes Pred, Register PredReg, int &Offset) { Offset = 0; MachineBasicBlock &MBB = *MBBI->getParent(); MachineBasicBlock::iterator BeginMBBI = MBB.begin(); @@ -1235,8 +1235,8 @@ findIncDecBefore(MachineBasicBlock::iterator MBBI, unsigned Reg, /// Searches for a increment or decrement of \p Reg after \p MBBI. static MachineBasicBlock::iterator -findIncDecAfter(MachineBasicBlock::iterator MBBI, unsigned Reg, - ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { +findIncDecAfter(MachineBasicBlock::iterator MBBI, Register Reg, + ARMCC::CondCodes Pred, Register PredReg, int &Offset) { Offset = 0; MachineBasicBlock &MBB = *MBBI->getParent(); MachineBasicBlock::iterator EndMBBI = MBB.end(); @@ -1270,7 +1270,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) { const MachineOperand &BaseOP = MI->getOperand(0); Register Base = BaseOP.getReg(); bool BaseKill = BaseOP.isKill(); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); unsigned Opcode = MI->getOpcode(); DebugLoc DL = MI->getDebugLoc(); @@ -1412,7 +1412,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) { if (MI->getOperand(0).getReg() == Base) return false; - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); int Bytes = getLSMultipleTransferSize(MI); MachineBasicBlock &MBB = *MI->getParent(); @@ -1525,7 +1525,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSDouble(MachineInstr &MI) const { if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base) return false; - unsigned PredReg; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); MachineBasicBlock::iterator MBBI(MI); MachineBasicBlock &MBB = *MI.getParent(); @@ -1602,7 +1602,7 @@ static bool isMemoryOp(const MachineInstr &MI) { // Don't touch volatile memory accesses - we may be changing their order. // TODO: We could allow unordered and monotonic atomics here, but we need to - // make sure the resulting ldm/stm is correctly marked as atomic. + // make sure the resulting ldm/stm is correctly marked as atomic. if (MMO.isVolatile() || MMO.isAtomic()) return false; @@ -1692,7 +1692,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB, assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) && "register offset not handled below"); int OffImm = getMemoryOpOffset(*MI); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); if (OddRegNum > EvenRegNum && OffImm == 0) { @@ -1792,7 +1792,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) { const MachineOperand &MO = MBBI->getOperand(0); Register Reg = MO.getReg(); Register Base = getLoadStoreBaseOp(*MBBI).getReg(); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg); int Offset = getMemoryOpOffset(*MBBI); if (CurrBase == 0) { @@ -2063,11 +2063,9 @@ namespace { private: bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, - unsigned &NewOpc, unsigned &EvenReg, - unsigned &OddReg, unsigned &BaseReg, - int &Offset, - unsigned &PredReg, ARMCC::CondCodes &Pred, - bool &isT2); + unsigned &NewOpc, Register &EvenReg, Register &OddReg, + Register &BaseReg, int &Offset, Register &PredReg, + ARMCC::CondCodes &Pred, bool &isT2); bool RescheduleOps(MachineBasicBlock *MBB, SmallVectorImpl &Ops, unsigned Base, bool isLd, @@ -2143,15 +2141,10 @@ static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, return AddedRegPressure.size() <= MemRegs.size() * 2; } -bool -ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, - DebugLoc &dl, unsigned &NewOpc, - unsigned &FirstReg, - unsigned &SecondReg, - unsigned &BaseReg, int &Offset, - unsigned &PredReg, - ARMCC::CondCodes &Pred, - bool &isT2) { +bool ARMPreAllocLoadStoreOpt::CanFormLdStDWord( + MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, + Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, + Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) { // Make sure we're allowed to generate LDRD/STRD. if (!STI->hasV5TEOps()) return false; @@ -2313,8 +2306,8 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, // to try to allocate a pair of registers that can form register pairs. MachineInstr *Op0 = Ops.back(); MachineInstr *Op1 = Ops[Ops.size()-2]; - unsigned FirstReg = 0, SecondReg = 0; - unsigned BaseReg = 0, PredReg = 0; + Register FirstReg, SecondReg; + Register BaseReg, PredReg; ARMCC::CondCodes Pred = ARMCC::AL; bool isT2 = false; unsigned NewOpc = 0; @@ -2416,7 +2409,7 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) { if (!isMemoryOp(MI)) continue; - unsigned PredReg = 0; + Register PredReg; if (getInstrPredicate(MI, PredReg) != ARMCC::AL) continue; diff --git a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp index 2de9829..c0214cf2 100644 --- a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp +++ b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp @@ -134,7 +134,7 @@ static bool StepOverPredicatedInstrs(MachineBasicBlock::instr_iterator &Iter, unsigned MaxSteps, unsigned &NumInstrsSteppedOver) { ARMVCC::VPTCodes NextPred = ARMVCC::None; - unsigned PredReg; + Register PredReg; NumInstrsSteppedOver = 0; while (Iter != EndIter) { @@ -261,7 +261,7 @@ bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) { while (MBIter != EndIter) { MachineInstr *MI = &*MBIter; - unsigned PredReg = 0; + Register PredReg; DebugLoc DL = MI->getDebugLoc(); ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg); diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp index 786fc78..5cdaa7f 100644 --- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -183,7 +183,7 @@ Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI, ++I; if (I != E) { - unsigned NPredReg = 0; + Register NPredReg; ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); if (NCC == CC || NCC == OCC) return true; @@ -199,7 +199,7 @@ bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) { while (MBBI != E) { MachineInstr *MI = &*MBBI; DebugLoc dl = MI->getDebugLoc(); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); if (CC == ARMCC::AL) { ++MBBI; @@ -239,7 +239,7 @@ bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) { MachineInstr *NMI = &*MBBI; MI = NMI; - unsigned NPredReg = 0; + Register NPredReg; ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); if (NCC == CC || NCC == OCC) { Mask |= ((NCC ^ CC) & 1) << Pos; diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index 0719b85..843ba47 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -66,7 +66,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, // If the first instruction of Tail is predicated, we may have to update // the IT instruction. - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); MachineBasicBlock::iterator MBBI = Tail; if (CC != ARMCC::AL) @@ -114,7 +114,7 @@ Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, return false; } - unsigned PredReg = 0; + Register PredReg; return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; } @@ -229,9 +229,9 @@ void Thumb2InstrInfo::expandLoadStackGuard( void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, - unsigned BaseReg, int NumBytes, - ARMCC::CondCodes Pred, unsigned PredReg, + const DebugLoc &dl, Register DestReg, + Register BaseReg, int NumBytes, + ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) { if (NumBytes == 0 && DestReg != BaseReg) { @@ -471,7 +471,7 @@ immediateOffsetOpcode(unsigned opcode) } bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, - unsigned FrameReg, int &Offset, + Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI) { unsigned Opcode = MI.getOpcode(); @@ -491,7 +491,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { Offset += MI.getOperand(FrameRegIdx+1).getImm(); - unsigned PredReg; + Register PredReg; if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL && !MI.definesRegister(ARM::CPSR)) { // Turn it into a move. @@ -706,7 +706,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, } ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI, - unsigned &PredReg) { + Register &PredReg) { unsigned Opc = MI.getOpcode(); if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) return ARMCC::AL; @@ -727,7 +727,7 @@ int llvm::findFirstVPTPredOperandIdx(const MachineInstr &MI) { } ARMVCC::VPTCodes llvm::getVPTInstrPredicate(const MachineInstr &MI, - unsigned &PredReg) { + Register &PredReg) { int PIdx = findFirstVPTPredOperandIdx(MI); if (PIdx == -1) { PredReg = 0; diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h index 583a091..b49a34f 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h @@ -67,15 +67,15 @@ private: /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical /// to llvm::getInstrPredicate except it returns AL for conditional branch /// instructions which are "predicated", but are not in IT blocks. -ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg); +ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg); // getVPTInstrPredicate: VPT analogue of that, plus a helper function // corresponding to MachineInstr::findFirstPredOperandIdx. int findFirstVPTPredOperandIdx(const MachineInstr &MI); ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, - unsigned &PredReg); + Register &PredReg); inline ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI) { - unsigned PredReg; + Register PredReg; return getVPTInstrPredicate(MI, PredReg); } } // namespace llvm diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index c732f03..d3e22b7 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -676,7 +676,7 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, default: break; case ARM::t2ADDSri: case ARM::t2ADDSrr: { - unsigned PredReg = 0; + Register PredReg; if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { switch (Opc) { default: break; @@ -718,7 +718,7 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); } case ARM::t2TEQrr: { - unsigned PredReg = 0; + Register PredReg; // Can only convert to eors if we're not in an IT block. if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) break; @@ -789,7 +789,7 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, // Check if it's possible / necessary to transfer the predicate. const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); bool SkipPred = false; if (Pred != ARMCC::AL) { @@ -882,7 +882,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, // Check if it's possible / necessary to transfer the predicate. const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); bool SkipPred = false; if (Pred != ARMCC::AL) { diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp index 2e6901d..966c0fd 100644 --- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp @@ -102,14 +102,13 @@ static void emitThumb2LoadConstPool(MachineBasicBlock &MBB, /// specified immediate. void ThumbRegisterInfo::emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, - ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { + const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, + ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { MachineFunction &MF = *MBB.getParent(); const ARMSubtarget &STI = MF.getSubtarget(); if (STI.isThumb1Only()) { - assert( - (isARMLowRegister(DestReg) || Register::isVirtualRegister(DestReg)) && - "Thumb1 does not have ldr to high register"); + assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && + "Thumb1 does not have ldr to high register"); return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, PredReg, MIFlags); } @@ -123,7 +122,7 @@ void ThumbRegisterInfo::emitLoadConstPool( /// constpool entry. static void emitThumbRegPlusImmInReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, + const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) { MachineFunction &MF = *MBB.getParent(); @@ -139,7 +138,7 @@ static void emitThumbRegPlusImmInReg( isSub = true; NumBytes = -NumBytes; } - unsigned LdReg = DestReg; + Register LdReg = DestReg; if (DestReg == ARM::SP) assert(BaseReg == ARM::SP && "Unexpected!"); if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg)) @@ -185,8 +184,8 @@ static void emitThumbRegPlusImmInReg( /// be too long. This is allowed to modify the condition flags. void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, - unsigned BaseReg, int NumBytes, + const DebugLoc &dl, Register DestReg, + Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags) { @@ -358,7 +357,7 @@ static unsigned convertToNonSPOpcode(unsigned Opcode) { bool ThumbRegisterInfo::rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, - unsigned FrameReg, int &Offset, + Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const { MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); @@ -427,8 +426,8 @@ bool ThumbRegisterInfo::rewriteFrameIndex(MachineBasicBlock::iterator II, return Offset == 0; } -void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, - int64_t Offset) const { +void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, + int64_t Offset) const { const MachineFunction &MF = *MI.getParent()->getParent(); const ARMSubtarget &STI = MF.getSubtarget(); if (!STI.isThumb1Only()) diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.h b/llvm/lib/Target/ARM/ThumbRegisterInfo.h index 08cf672..e05a24d 100644 --- a/llvm/lib/Target/ARM/ThumbRegisterInfo.h +++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.h @@ -38,18 +38,18 @@ public: /// specified immediate. void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, + const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred = ARMCC::AL, - unsigned PredReg = 0, + Register PredReg = Register(), unsigned MIFlags = MachineInstr::NoFlags) const override; // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be // however much remains to be handled. Return 'true' if no further // work is required. bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, - unsigned FrameReg, int &Offset, + Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const; - void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp index 5703f58..f6f43da 100644 --- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp @@ -53,12 +53,10 @@ bool Mips16RegisterInfo::useFPForScavengingIndex return false; } -bool Mips16RegisterInfo::saveScavengerRegister - (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - MachineBasicBlock::iterator &UseMI, - const TargetRegisterClass *RC, - unsigned Reg) const { +bool Mips16RegisterInfo::saveScavengerRegister( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, + Register Reg) const { DebugLoc DL; const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo(); TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); @@ -96,7 +94,7 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, // 3. Locations for callee-saved registers. // Everything else is referenced relative to whatever register // getFrameRegister() returns. - unsigned FrameReg; + Register FrameReg; if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) FrameReg = Mips::SP; diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.h b/llvm/lib/Target/Mips/Mips16RegisterInfo.h index fca78b4..0da1eee 100644 --- a/llvm/lib/Target/Mips/Mips16RegisterInfo.h +++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.h @@ -29,10 +29,10 @@ public: bool useFPForScavengingIndex(const MachineFunction &MF) const override; bool saveScavengerRegister(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - MachineBasicBlock::iterator &UseMI, - const TargetRegisterClass *RC, - unsigned Reg) const override; + MachineBasicBlock::iterator I, + MachineBasicBlock::iterator &UseMI, + const TargetRegisterClass *RC, + Register Reg) const override; const TargetRegisterClass *intRegClass(unsigned Size) const override; diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index c637fb9..4fcfb79 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -649,7 +649,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, // If the saved register wasn't CR0, shift the bits left so that they are in // CR0's slot. if (SrcReg != PPC::CR0) { - unsigned Reg1 = Reg; + Register Reg1 = Reg; Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); // rlwinm rA, rA, ShiftBits, 0, 31. @@ -694,7 +694,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, // If the reloaded register isn't CR0, shift the bits right so that they are // in the right CR's slot. if (DestReg != PPC::CR0) { - unsigned Reg1 = Reg; + Register Reg1 = Reg; Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); unsigned ShiftBits = getEncodingValue(DestReg)*4; @@ -798,7 +798,7 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, // If the saved register wasn't CR0LT, shift the bits left so that the bit // to store is the first one. Mask all but that bit. - unsigned Reg1 = Reg; + Register Reg1 = Reg; Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); // rlwinm rA, rA, ShiftBits, 0, 0. @@ -924,7 +924,7 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, } bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, - unsigned Reg, int &FrameIdx) const { + Register Reg, int &FrameIdx) const { // For the nonvolatile condition registers (CR2, CR3, CR4) return true to // prevent allocating an additional frame slot. // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8, @@ -1103,7 +1103,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; - unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), + Register SRegHi = MF.getRegInfo().createVirtualRegister(RC), SReg = MF.getRegInfo().createVirtualRegister(RC); // Insert a set of rA with the full offset value before the ld, st, or add @@ -1226,10 +1226,10 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { /// Insert defining instruction(s) for BaseReg to /// be a pointer to FrameIdx at the beginning of the basic block. -void PPCRegisterInfo:: -materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, int FrameIdx, - int64_t Offset) const { +void PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, + Register BaseReg, + int FrameIdx, + int64_t Offset) const { unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; MachineBasicBlock::iterator Ins = MBB->begin(); @@ -1248,7 +1248,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB, .addFrameIndex(FrameIdx).addImm(Offset); } -void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, +void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const { unsigned FIOperandNum = 0; while (!MI.getOperand(FIOperandNum).isFI()) { @@ -1273,7 +1273,7 @@ void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, } bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, - unsigned BaseReg, + Register BaseReg, int64_t Offset) const { unsigned FIOperandNum = 0; while (!MI->getOperand(FIOperandNum).isFI()) { diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h index b9d0354..4d7e0ac 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h @@ -121,7 +121,7 @@ public: void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const; - bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, + bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, @@ -129,12 +129,12 @@ public: // Support for virtual base registers. bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, - unsigned BaseReg, int FrameIdx, + void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, + int FrameIdx, int64_t Offset) const override; - void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; - bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, + bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override; // Debug information queries. diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 51044a2..fd234c4 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -123,7 +123,7 @@ static const std::map FixedCSRFIMap = { }; bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, - unsigned Reg, + Register Reg, int &FrameIdx) const { const auto *RVFI = MF.getInfo(); if (!RVFI->useSaveRestoreLibCalls()) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h index 23b7465..ffbb60a 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -37,7 +37,7 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo { const uint32_t *getNoPreservedMask() const override; - bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, + bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override; void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp index bb79eb3..e655bf8 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -73,13 +73,10 @@ static void addHints(ArrayRef Order, Hints.push_back(Reg); } -bool -SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg, - ArrayRef Order, - SmallVectorImpl &Hints, - const MachineFunction &MF, - const VirtRegMap *VRM, - const LiveRegMatrix *Matrix) const { +bool SystemZRegisterInfo::getRegAllocationHints( + Register VirtReg, ArrayRef Order, + SmallVectorImpl &Hints, const MachineFunction &MF, + const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const { const MachineRegisterInfo *MRI = &MF.getRegInfo(); const SystemZSubtarget &Subtarget = MF.getSubtarget(); const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); @@ -134,11 +131,11 @@ SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg, } if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) { - SmallVector Worklist; - SmallSet DoneRegs; + SmallVector Worklist; + SmallSet DoneRegs; Worklist.push_back(VirtReg); while (Worklist.size()) { - unsigned Reg = Worklist.pop_back_val(); + Register Reg = Worklist.pop_back_val(); if (!DoneRegs.insert(Reg).second) continue; diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h index 5ee5ac1..9f2cca0 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h @@ -58,11 +58,9 @@ public: const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override; - bool getRegAllocationHints(unsigned VirtReg, - ArrayRef Order, + bool getRegAllocationHints(Register VirtReg, ArrayRef Order, SmallVectorImpl &Hints, - const MachineFunction &MF, - const VirtRegMap *VRM, + const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override; // Override TargetRegisterInfo.h. diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 1c9295c..7834632 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -661,7 +661,7 @@ bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const { } bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, - unsigned Reg, int &FrameIdx) const { + Register Reg, int &FrameIdx) const { // Since X86 defines assignCalleeSavedSpillSlots which always return true // this function neither used nor tested. llvm_unreachable("Unused function on X86. Otherwise need a test case."); diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h index 1c933f4..3435c0a 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.h +++ b/llvm/lib/Target/X86/X86RegisterInfo.h @@ -121,7 +121,7 @@ public: bool canRealignStack(const MachineFunction &MF) const override; - bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, + bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override; void eliminateFrameIndex(MachineBasicBlock::iterator MI, -- 2.7.4