From 5fdbc4a23e1a15b90e399a7586bece0b47e408d7 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Mon, 6 Mar 2023 11:28:46 +0200
Subject: [PATCH] intel/isl: disable TILE64 for YCRCB formats
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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21723>
---
 src/intel/isl/isl_gfx12.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c
index 959139c..79d89c9 100644
--- a/src/intel/isl/isl_gfx12.c
+++ b/src/intel/isl/isl_gfx12.c
@@ -74,6 +74,13 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
    if (info->dim != ISL_SURF_DIM_2D)
       *flags &= ~ISL_TILING_64_BIT;
 
+   /* TILE64 does not work with YCRCB formats, according to bspec 58767:
+    * "Packed YUV surface formats such as YCRCB_NORMAL, YCRCB_SWAPUVY etc.
+    * will not support as Tile64"
+    */
+   if (isl_format_is_yuv(info->format))
+      *flags &= ~ISL_TILING_64_BIT;
+
    /* From RENDER_SURFACE_STATE::NumberofMultisamples,
     *
     *    This field must not be programmed to anything other than
-- 
2.7.4