From 5fd0d27280da8e7834a19fdb51411b2c98a72a4f Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 30 Nov 2022 18:50:32 +0200 Subject: [PATCH] intel/ds: trace a couple of more pipe control flags Reviewed-by: Ian Romanick Part-of: --- src/intel/ds/intel_driver_ds.h | 1 + src/intel/ds/intel_tracepoints.py | 31 ++++++++++++++++++------------- src/intel/vulkan/anv_utrace.c | 1 + 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/src/intel/ds/intel_driver_ds.h b/src/intel/ds/intel_driver_ds.h index ca03c65..0b0bd7c 100644 --- a/src/intel/ds/intel_driver_ds.h +++ b/src/intel/ds/intel_driver_ds.h @@ -56,6 +56,7 @@ enum intel_ds_stall_flag { INTEL_DS_DEPTH_STALL_BIT = BITFIELD_BIT(11), INTEL_DS_CS_STALL_BIT = BITFIELD_BIT(12), INTEL_DS_UNTYPED_DATAPORT_CACHE_FLUSH_BIT = BITFIELD_BIT(13), + INTEL_DS_PSS_STALL_SYNC_BIT = BITFIELD_BIT(14), }; /* Convert internal driver PIPE_CONTROL stall bits to intel_ds_stall_flag. */ diff --git a/src/intel/ds/intel_tracepoints.py b/src/intel/ds/intel_tracepoints.py index 9830cbc..2ad7a37 100644 --- a/src/intel/ds/intel_tracepoints.py +++ b/src/intel/ds/intel_tracepoints.py @@ -133,23 +133,28 @@ def define_tracepoints(args): exprs.append('(__entry->flags & INTEL_DS_{0}_BIT) ? "+{1}" : ""'.format(a[0], a[1])) fmt += ' : %s' exprs.append('__entry->reason ? __entry->reason : "unknown"') + # To printout flags + # fmt += '(0x%08x)' + # exprs.append('__entry->flags') fmt = [fmt] fmt += exprs return fmt - stall_flags = [['DEPTH_CACHE_FLUSH', 'depth_flush'], - ['DATA_CACHE_FLUSH', 'dc_flush'], - ['HDC_PIPELINE_FLUSH', 'hdc_flush'], - ['RENDER_TARGET_CACHE_FLUSH', 'rt_flush'], - ['TILE_CACHE_FLUSH', 'tile_flush'], - ['STATE_CACHE_INVALIDATE', 'state_inval'], - ['CONST_CACHE_INVALIDATE', 'const_inval'], - ['VF_CACHE_INVALIDATE', 'vf_inval'], - ['TEXTURE_CACHE_INVALIDATE', 'tex_inval'], - ['INST_CACHE_INVALIDATE', 'ic_inval'], - ['STALL_AT_SCOREBOARD', 'pb_stall'], - ['DEPTH_STALL', 'depth_stall'], - ['CS_STALL', 'cs_stall']] + stall_flags = [['DEPTH_CACHE_FLUSH', 'depth_flush'], + ['DATA_CACHE_FLUSH', 'dc_flush'], + ['HDC_PIPELINE_FLUSH', 'hdc_flush'], + ['RENDER_TARGET_CACHE_FLUSH', 'rt_flush'], + ['TILE_CACHE_FLUSH', 'tile_flush'], + ['STATE_CACHE_INVALIDATE', 'state_inval'], + ['CONST_CACHE_INVALIDATE', 'const_inval'], + ['VF_CACHE_INVALIDATE', 'vf_inval'], + ['TEXTURE_CACHE_INVALIDATE', 'tex_inval'], + ['INST_CACHE_INVALIDATE', 'ic_inval'], + ['STALL_AT_SCOREBOARD', 'pb_stall'], + ['DEPTH_STALL', 'depth_stall'], + ['CS_STALL', 'cs_stall'], + ['UNTYPED_DATAPORT_CACHE_FLUSH', 'udp_flush'], + ['PSS_STALL_SYNC', 'pss_stall']] begin_end_tp('stall', tp_args=[ArgStruct(type='uint32_t', var='flags'), diff --git a/src/intel/vulkan/anv_utrace.c b/src/intel/vulkan/anv_utrace.c index 898c918..3646f43 100644 --- a/src/intel/vulkan/anv_utrace.c +++ b/src/intel/vulkan/anv_utrace.c @@ -317,6 +317,7 @@ anv_pipe_flush_bit_to_ds_stall_flag(enum anv_pipe_bits bits) { .anv = ANV_PIPE_HDC_PIPELINE_FLUSH_BIT, .ds = INTEL_DS_HDC_PIPELINE_FLUSH_BIT, }, { .anv = ANV_PIPE_STALL_AT_SCOREBOARD_BIT, .ds = INTEL_DS_STALL_AT_SCOREBOARD_BIT, }, { .anv = ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, .ds = INTEL_DS_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, }, + { .anv = ANV_PIPE_PSS_STALL_SYNC_BIT, .ds = INTEL_DS_PSS_STALL_SYNC_BIT, }, }; enum intel_ds_stall_flag ret = 0; -- 2.7.4