From 5fcb5d77599e2b028dd8b7b8a3a7853701838e0c Mon Sep 17 00:00:00 2001 From: Yeting Kuo Date: Mon, 5 Sep 2022 21:57:22 +0800 Subject: [PATCH] [RISCV] Add assertion of hasVecPolicyOp to catch masked intrinsic without policy operand. The original code may have incorrect result if there is a masked instruction without policy operand to make us set its policy to TUMU. The patch adds an assertion to catch the instruction. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D133302 --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index ac57716..52dd41d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2697,14 +2697,15 @@ bool RISCVDAGToDAGISel::doPeepholeMergeVVMFold() { SDLoc DL(N); unsigned MaskedOpc = Info->MaskedPseudo; + assert(RISCVII::hasVecPolicyOp(TII->get(MaskedOpc).TSFlags) && + "Expected instructions with mask have policy operand."); + SmallVector Ops; Ops.push_back(Merge); Ops.append(True->op_begin(), True->op_begin() + TrueVLIndex); Ops.append({Mask, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)}); - - if (RISCVII::hasVecPolicyOp(TII->get(MaskedOpc).TSFlags)) - Ops.push_back( - CurDAG->getTargetConstant(/* TUMU */ 0, DL, Subtarget->getXLenVT())); + Ops.push_back( + CurDAG->getTargetConstant(/* TUMU */ 0, DL, Subtarget->getXLenVT())); // Result node should have chain operand of True. if (HasChainOp) -- 2.7.4