From 5fb033a3368d78cc1d2460cc4db5880398513b26 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 18 May 2018 22:05:25 +0800 Subject: [PATCH] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch conditional build in order this file can by shared across other SOCFPGAs. Signed-off-by: Chin Liang See Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/misc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 7bedcb3..fca8650 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -22,8 +22,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif struct bsel bsel_str[] = { { "rsvd", "Reserved", }, @@ -52,6 +54,7 @@ void enable_caches(void) #endif } +#ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { /* Disable the L2 cache */ @@ -72,6 +75,7 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -- 2.7.4