From 5f9fc5ad7efe2840d3170775768fb85686d94869 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Mon, 29 Mar 2010 19:23:55 +0000 Subject: [PATCH] Compile pflash_cfi02 only once Push TARGET_WORDS_BIGENDIAN dependency to board level. Signed-off-by: Blue Swirl --- Makefile.objs | 1 + Makefile.target | 6 +- default-configs/arm-softmmu.mak | 1 + default-configs/cris-softmmu.mak | 1 + default-configs/ppc-softmmu.mak | 1 + default-configs/ppc64-softmmu.mak | 1 + default-configs/ppcemb-softmmu.mak | 1 + hw/etraxfs.c | 2 +- hw/flash.h | 3 +- hw/musicpal.c | 12 ++- hw/pflash_cfi02.c | 190 ++++++++++++++++++++++++------------- hw/ppc405_boards.c | 9 +- 12 files changed, 154 insertions(+), 74 deletions(-) diff --git a/Makefile.objs b/Makefile.objs index cd1e721..f4e1e3d 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -135,6 +135,7 @@ hw-obj-y += watchdog.o hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o hw-obj-$(CONFIG_ECC) += ecc.o hw-obj-$(CONFIG_NAND) += nand.o +hw-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o hw-obj-$(CONFIG_M48T59) += m48t59.o hw-obj-$(CONFIG_ESCC) += escc.o diff --git a/Makefile.target b/Makefile.target index ee027c8..536c6fb 100644 --- a/Makefile.target +++ b/Makefile.target @@ -202,7 +202,7 @@ obj-ppc-y += heathrow_pic.o grackle_pci.o ppc_oldworld.o # NewWorld PowerMac obj-ppc-y += unin_pci.o ppc_newworld.o dec_pci.o # PowerPC 4xx boards -obj-ppc-y += pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o +obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o obj-ppc-y += ppc440.o ppc440_bamboo.o # PowerPC E500 boards obj-ppc-y += ppce500_pci.o ppce500_mpc8544ds.o @@ -239,8 +239,6 @@ obj-cris-y += etraxfs_eth.o obj-cris-y += etraxfs_timer.o obj-cris-y += etraxfs_ser.o -obj-cris-y += pflash_cfi02.o - ifeq ($(TARGET_ARCH), sparc64) obj-sparc-y = sun4u.o pckbd.o apb_pci.o obj-sparc-y += vga.o @@ -268,7 +266,7 @@ obj-arm-y += omap2.o omap_dss.o soc_dma.o obj-arm-y += omap_sx1.o palm.o tsc210x.o obj-arm-y += nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o obj-arm-y += mst_fpga.o mainstone.o -obj-arm-y += musicpal.o pflash_cfi02.o bitbang_i2c.o marvell_88w8618_audio.o +obj-arm-y += musicpal.o bitbang_i2c.o marvell_88w8618_audio.o obj-arm-y += framebuffer.o obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index dc027c7..04ce487 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -26,3 +26,4 @@ CONFIG_LAN9118=y CONFIG_SMC91C111=y CONFIG_DS1338=y CONFIG_VIRTIO_PCI=y +CONFIG_PFLASH_CFI02=y diff --git a/default-configs/cris-softmmu.mak b/default-configs/cris-softmmu.mak index b8c281b..e0d2cab 100644 --- a/default-configs/cris-softmmu.mak +++ b/default-configs/cris-softmmu.mak @@ -3,3 +3,4 @@ CONFIG_NAND=y CONFIG_PTIMER=y CONFIG_VIRTIO_PCI=y +CONFIG_PFLASH_CFI02=y diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak index e926255..15530be 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -17,3 +17,4 @@ CONFIG_IDE_CMD646=y CONFIG_NE2000_ISA=y CONFIG_SOUND=y CONFIG_VIRTIO_PCI=y +CONFIG_PFLASH_CFI02=y diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak index 28ef9df..6b90525 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -17,3 +17,4 @@ CONFIG_IDE_CMD646=y CONFIG_NE2000_ISA=y CONFIG_SOUND=y CONFIG_VIRTIO_PCI=y +CONFIG_PFLASH_CFI02=y diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-softmmu.mak index 3ba8e70..ceb67b3 100644 --- a/default-configs/ppcemb-softmmu.mak +++ b/default-configs/ppcemb-softmmu.mak @@ -17,3 +17,4 @@ CONFIG_IDE_CMD646=y CONFIG_NE2000_ISA=y CONFIG_SOUND=y CONFIG_VIRTIO_PCI=y +CONFIG_PFLASH_CFI02=y diff --git a/hw/etraxfs.c b/hw/etraxfs.c index 7405db4..b88d00a 100644 --- a/hw/etraxfs.c +++ b/hw/etraxfs.c @@ -92,7 +92,7 @@ void bareetraxfs_init (ram_addr_t ram_size, dinfo ? dinfo->bdrv : NULL, (64 * 1024), FLASH_SIZE >> 16, 1, 2, 0x0000, 0x0000, 0x0000, 0x0000, - 0x555, 0x2aa); + 0x555, 0x2aa, 0); cpu_irq = cris_pic_init_cpu(env); dev = qdev_create(NULL, "etraxfs,pic"); /* FIXME: Is there a proper way to signal vectors to the CPU core? */ diff --git a/hw/flash.h b/hw/flash.h index 69aef8c..d6db468 100644 --- a/hw/flash.h +++ b/hw/flash.h @@ -14,7 +14,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, int nb_blocs, int nb_mappings, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, - uint16_t unlock_addr0, uint16_t unlock_addr1); + uint16_t unlock_addr0, uint16_t unlock_addr1, + int be); /* nand.c */ typedef struct NANDFlashState NANDFlashState; diff --git a/hw/musicpal.c b/hw/musicpal.c index 7fc9fb3..ebd933e 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -1558,12 +1558,22 @@ static void musicpal_init(ram_addr_t ram_size, * 0xFF800000 (if there is 8 MB flash). So remap flash access if the * image is smaller than 32 MB. */ +#ifdef TARGET_WORDS_BIGENDIAN pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size), dinfo->bdrv, 0x10000, (flash_size + 0xffff) >> 16, MP_FLASH_SIZE_MAX / flash_size, 2, 0x00BF, 0x236D, 0x0000, 0x0000, - 0x5555, 0x2AAA); + 0x5555, 0x2AAA, 1); +#else + pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size), + dinfo->bdrv, 0x10000, + (flash_size + 0xffff) >> 16, + MP_FLASH_SIZE_MAX / flash_size, + 2, 0x00BF, 0x236D, 0x0000, 0x0000, + 0x5555, 0x2AAA, 0); +#endif + } sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 50b4c6c..bd6397b 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -103,7 +103,8 @@ static void pflash_timer (void *opaque) pfl->cmd = 0; } -static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, int width) +static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, + int width, int be) { target_phys_addr_t boff; uint32_t ret; @@ -140,27 +141,27 @@ static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, int width // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret); break; case 2: -#if defined(TARGET_WORDS_BIGENDIAN) - ret = p[offset] << 8; - ret |= p[offset + 1]; -#else - ret = p[offset]; - ret |= p[offset + 1] << 8; -#endif + if (be) { + ret = p[offset] << 8; + ret |= p[offset + 1]; + } else { + ret = p[offset]; + ret |= p[offset + 1] << 8; + } // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret); break; case 4: -#if defined(TARGET_WORDS_BIGENDIAN) - ret = p[offset] << 24; - ret |= p[offset + 1] << 16; - ret |= p[offset + 2] << 8; - ret |= p[offset + 3]; -#else - ret = p[offset]; - ret |= p[offset + 1] << 8; - ret |= p[offset + 2] << 16; - ret |= p[offset + 3] << 24; -#endif + if (be) { + ret = p[offset] << 24; + ret |= p[offset + 1] << 16; + ret |= p[offset + 2] << 8; + ret |= p[offset + 3]; + } else { + ret = p[offset]; + ret |= p[offset + 1] << 8; + ret |= p[offset + 2] << 16; + ret |= p[offset + 3] << 24; + } // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret); break; } @@ -223,7 +224,7 @@ static void pflash_update(pflash_t *pfl, int offset, } static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, - uint32_t value, int width) + uint32_t value, int width, int be) { target_phys_addr_t boff; uint8_t *p; @@ -316,27 +317,27 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, pflash_update(pfl, offset, 1); break; case 2: -#if defined(TARGET_WORDS_BIGENDIAN) - p[offset] &= value >> 8; - p[offset + 1] &= value; -#else - p[offset] &= value; - p[offset + 1] &= value >> 8; -#endif + if (be) { + p[offset] &= value >> 8; + p[offset + 1] &= value; + } else { + p[offset] &= value; + p[offset + 1] &= value >> 8; + } pflash_update(pfl, offset, 2); break; case 4: -#if defined(TARGET_WORDS_BIGENDIAN) - p[offset] &= value >> 24; - p[offset + 1] &= value >> 16; - p[offset + 2] &= value >> 8; - p[offset + 3] &= value; -#else - p[offset] &= value; - p[offset + 1] &= value >> 8; - p[offset + 2] &= value >> 16; - p[offset + 3] &= value >> 24; -#endif + if (be) { + p[offset] &= value >> 24; + p[offset + 1] &= value >> 16; + p[offset + 2] &= value >> 8; + p[offset + 3] &= value; + } else { + p[offset] &= value; + p[offset + 1] &= value >> 8; + p[offset + 2] &= value >> 16; + p[offset + 3] &= value >> 24; + } pflash_update(pfl, offset, 4); break; } @@ -451,57 +452,110 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, } -static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) +{ + return pflash_read(opaque, addr, 1, 1); +} + +static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) +{ + return pflash_read(opaque, addr, 1, 0); +} + +static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) +{ + pflash_t *pfl = opaque; + + return pflash_read(pfl, addr, 2, 1); +} + +static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) +{ + pflash_t *pfl = opaque; + + return pflash_read(pfl, addr, 2, 0); +} + +static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) { - return pflash_read(opaque, addr, 1); + pflash_t *pfl = opaque; + + return pflash_read(pfl, addr, 4, 1); } -static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) { pflash_t *pfl = opaque; - return pflash_read(pfl, addr, 2); + return pflash_read(pfl, addr, 4, 0); +} + +static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + pflash_write(opaque, addr, value, 1, 1); } -static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) +static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + pflash_write(opaque, addr, value, 1, 0); +} + +static void pflash_writew_be(void *opaque, target_phys_addr_t addr, + uint32_t value) { pflash_t *pfl = opaque; - return pflash_read(pfl, addr, 4); + pflash_write(pfl, addr, value, 2, 1); } -static void pflash_writeb (void *opaque, target_phys_addr_t addr, - uint32_t value) +static void pflash_writew_le(void *opaque, target_phys_addr_t addr, + uint32_t value) { - pflash_write(opaque, addr, value, 1); + pflash_t *pfl = opaque; + + pflash_write(pfl, addr, value, 2, 0); } -static void pflash_writew (void *opaque, target_phys_addr_t addr, - uint32_t value) +static void pflash_writel_be(void *opaque, target_phys_addr_t addr, + uint32_t value) { pflash_t *pfl = opaque; - pflash_write(pfl, addr, value, 2); + pflash_write(pfl, addr, value, 4, 1); } -static void pflash_writel (void *opaque, target_phys_addr_t addr, - uint32_t value) +static void pflash_writel_le(void *opaque, target_phys_addr_t addr, + uint32_t value) { pflash_t *pfl = opaque; - pflash_write(pfl, addr, value, 4); + pflash_write(pfl, addr, value, 4, 0); } -static CPUWriteMemoryFunc * const pflash_write_ops[] = { - &pflash_writeb, - &pflash_writew, - &pflash_writel, +static CPUWriteMemoryFunc * const pflash_write_ops_be[] = { + &pflash_writeb_be, + &pflash_writew_be, + &pflash_writel_be, }; -static CPUReadMemoryFunc * const pflash_read_ops[] = { - &pflash_readb, - &pflash_readw, - &pflash_readl, +static CPUReadMemoryFunc * const pflash_read_ops_be[] = { + &pflash_readb_be, + &pflash_readw_be, + &pflash_readl_be, +}; + +static CPUWriteMemoryFunc * const pflash_write_ops_le[] = { + &pflash_writeb_le, + &pflash_writew_le, + &pflash_writel_le, +}; + +static CPUReadMemoryFunc * const pflash_read_ops_le[] = { + &pflash_readb_le, + &pflash_readw_le, + &pflash_readl_le, }; /* Count trailing zeroes of a 32 bits quantity */ @@ -543,7 +597,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, int nb_blocs, int nb_mappings, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, - uint16_t unlock_addr0, uint16_t unlock_addr1) + uint16_t unlock_addr0, uint16_t unlock_addr1, + int be) { pflash_t *pfl; int32_t chip_len; @@ -559,8 +614,15 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, pfl = qemu_mallocz(sizeof(pflash_t)); /* FIXME: Allocate ram ourselves. */ pfl->storage = qemu_get_ram_ptr(off); - pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops, - pfl); + if (be) { + pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, + pflash_write_ops_be, + pfl); + } else { + pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, + pflash_write_ops_le, + pfl); + } pfl->off = off; pfl->base = base; pfl->chip_len = chip_len; diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 735adc9..f40d618 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -228,7 +228,8 @@ static void ref405ep_init (ram_addr_t ram_size, #endif pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, dinfo->bdrv, 65536, fl_sectors, 1, - 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, + 1); fl_idx++; } else #endif @@ -542,7 +543,8 @@ static void taihu_405ep_init(ram_addr_t ram_size, #endif pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, dinfo->bdrv, 65536, fl_sectors, 1, - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, + 1); fl_idx++; } else #endif @@ -584,7 +586,8 @@ static void taihu_405ep_init(ram_addr_t ram_size, bios_offset = qemu_ram_alloc(bios_size); pflash_cfi02_register(0xfc000000, bios_offset, dinfo->bdrv, 65536, fl_sectors, 1, - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, + 1); fl_idx++; } /* Register CLPD & LCD display */ -- 2.7.4