From 5f9489b754055da979876bcb5a357310251c6b87 Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Wed, 3 Mar 2021 16:17:37 +0800 Subject: [PATCH] [X86] Refine "Support -march=alderlake" Refine "Support -march=alderlake" Compare with tremont, it includes 25 more new features. They are adx, aes, avx, avx2, avxvnni, bmi, bmi2, cldemote, f16c, fma, hreset, invpcid, kl, lzcnt, movdir64b, movdiri, pclmulqdq, pconfig, pku, serialize, shstk, vaes, vpclmulqdq, waitpkg, widekl. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D97832 --- clang/test/Preprocessor/predefined-arch-macros.c | 39 ++++++++++++++++++++++++ llvm/lib/Support/X86TargetParser.cpp | 9 ++++-- llvm/lib/Target/X86/X86.td | 36 +++++++++++++++------- 3 files changed, 70 insertions(+), 14 deletions(-) diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index 254ca60..48874fd 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -1791,32 +1791,53 @@ // CHECK_ADL_M32: #define __BMI__ 1 // CHECK_ADL_M32: #define __CLDEMOTE__ 1 // CHECK_ADL_M32: #define __CLFLUSHOPT__ 1 +// CHECK_ADL_M32: #define __CLWB__ 1 // CHECK_ADL_M32: #define __F16C__ 1 // CHECK_ADL_M32: #define __FMA__ 1 +// CHECK_ADL_M32: #define __FSGSBASE__ 1 +// CHECK_ADL_M32: #define __FXSR__ 1 +// CHECK_ADL_M32: #define __GFNI__ 1 // CHECK_ADL_M32: #define __HRESET__ 1 // CHECK_ADL_M32: #define __INVPCID__ 1 +// CHECK_ADL_M32: #define __KL__ 1 // CHECK_ADL_M32: #define __LZCNT__ 1 // CHECK_ADL_M32: #define __MMX__ 1 // CHECK_ADL_M32: #define __MOVBE__ 1 +// CHECK_ADL_M32: #define __MOVDIR64B__ 1 +// CHECK_ADL_M32: #define __MOVDIRI__ 1 // CHECK_ADL_M32: #define __PCLMUL__ 1 +// CHECK_ADL_M32: #define __PCONFIG__ 1 +// CHECK_ADL_M32: #define __PKU__ 1 // CHECK_ADL_M32: #define __POPCNT__ 1 // CHECK_ADL_M32: #define __PRFCHW__ 1 // CHECK_ADL_M32: #define __PTWRITE__ 1 +// CHECK_ADL_M32: #define __RDPID__ 1 // CHECK_ADL_M32: #define __RDRND__ 1 // CHECK_ADL_M32: #define __RDSEED__ 1 // CHECK_ADL_M32: #define __SERIALIZE__ 1 // CHECK_ADL_M32: #define __SGX__ 1 +// CHECK_ADL_M32: #define __SHA__ 1 +// CHECK_ADL_M32: #define __SHSTK__ 1 // CHECK_ADL_M32: #define __SSE2__ 1 // CHECK_ADL_M32: #define __SSE3__ 1 // CHECK_ADL_M32: #define __SSE4_1__ 1 // CHECK_ADL_M32: #define __SSE4_2__ 1 +// CHECK_ADL_M32: #define __SSE_MATH__ 1 // CHECK_ADL_M32: #define __SSE__ 1 // CHECK_ADL_M32: #define __SSSE3__ 1 +// CHECK_ADL_M32: #define __VAES__ 1 +// CHECK_ADL_M32: #define __VPCLMULQDQ__ 1 // CHECK_ADL_M32: #define __WAITPKG__ 1 +// CHECK_ADL_M32: #define __WIDEKL__ 1 // CHECK_ADL_M32: #define __XSAVEC__ 1 // CHECK_ADL_M32: #define __XSAVEOPT__ 1 // CHECK_ADL_M32: #define __XSAVES__ 1 // CHECK_ADL_M32: #define __XSAVE__ 1 +// CHECK_ADL_M32: #define __corei7 1 +// CHECK_ADL_M32: #define __corei7__ 1 +// CHECK_ADL_M32: #define __i386 1 +// CHECK_ADL_M32: #define __i386__ 1 +// CHECK_ADL_M32: #define __tune_corei7__ 1 // CHECK_ADL_M32: #define i386 1 // RUN: %clang -march=alderlake -m64 -E -dM %s -o - 2>&1 \ @@ -1832,21 +1853,33 @@ // CHECK_ADL_M64: #define __BMI__ 1 // CHECK_ADL_M64: #define __CLDEMOTE__ 1 // CHECK_ADL_M64: #define __CLFLUSHOPT__ 1 +// CHECK_ADL_M64: #define __CLWB__ 1 // CHECK_ADL_M64: #define __F16C__ 1 // CHECK_ADL_M64: #define __FMA__ 1 +// CHECK_ADL_M64: #define __FSGSBASE__ 1 +// CHECK_ADL_M64: #define __FXSR__ 1 +// CHECK_ADL_M64: #define __GFNI__ 1 // CHECK_ADL_M64: #define __HRESET__ 1 // CHECK_ADL_M64: #define __INVPCID__ 1 +// CHECK_ADL_M64: #define __KL__ 1 // CHECK_ADL_M64: #define __LZCNT__ 1 // CHECK_ADL_M64: #define __MMX__ 1 // CHECK_ADL_M64: #define __MOVBE__ 1 +// CHECK_ADL_M64: #define __MOVDIR64B__ 1 +// CHECK_ADL_M64: #define __MOVDIRI__ 1 // CHECK_ADL_M64: #define __PCLMUL__ 1 +// CHECK_ADL_M64: #define __PCONFIG__ 1 +// CHECK_ADL_M64: #define __PKU__ 1 // CHECK_ADL_M64: #define __POPCNT__ 1 // CHECK_ADL_M64: #define __PRFCHW__ 1 // CHECK_ADL_M64: #define __PTWRITE__ 1 +// CHECK_ADL_M64: #define __RDPID__ 1 // CHECK_ADL_M64: #define __RDRND__ 1 // CHECK_ADL_M64: #define __RDSEED__ 1 // CHECK_ADL_M64: #define __SERIALIZE__ 1 // CHECK_ADL_M64: #define __SGX__ 1 +// CHECK_ADL_M64: #define __SHA__ 1 +// CHECK_ADL_M64: #define __SHSTK__ 1 // CHECK_ADL_M64: #define __SSE2_MATH__ 1 // CHECK_ADL_M64: #define __SSE2__ 1 // CHECK_ADL_M64: #define __SSE3__ 1 @@ -1855,13 +1888,19 @@ // CHECK_ADL_M64: #define __SSE_MATH__ 1 // CHECK_ADL_M64: #define __SSE__ 1 // CHECK_ADL_M64: #define __SSSE3__ 1 +// CHECK_ADL_M64: #define __VAES__ 1 +// CHECK_ADL_M64: #define __VPCLMULQDQ__ 1 // CHECK_ADL_M64: #define __WAITPKG__ 1 +// CHECK_ADL_M64: #define __WIDEKL__ 1 // CHECK_ADL_M64: #define __XSAVEC__ 1 // CHECK_ADL_M64: #define __XSAVEOPT__ 1 // CHECK_ADL_M64: #define __XSAVES__ 1 // CHECK_ADL_M64: #define __XSAVE__ 1 // CHECK_ADL_M64: #define __amd64 1 // CHECK_ADL_M64: #define __amd64__ 1 +// CHECK_ADL_M64: #define __corei7 1 +// CHECK_ADL_M64: #define __corei7__ 1 +// CHECK_ADL_M64: #define __tune_corei7__ 1 // CHECK_ADL_M64: #define __x86_64 1 // CHECK_ADL_M64: #define __x86_64__ 1 diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index d738511..6355fd1 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -205,9 +205,6 @@ constexpr FeatureBitset FeaturesSapphireRapids = FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG | FeatureAVXVNNI; -constexpr FeatureBitset FeaturesAlderlake = - FeaturesSkylakeClient | FeatureCLDEMOTE | FeatureHRESET | FeaturePTWRITE | - FeatureSERIALIZE | FeatureWAITPKG | FeatureAVXVNNI; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. @@ -223,6 +220,12 @@ constexpr FeatureBitset FeaturesGoldmontPlus = FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; constexpr FeatureBitset FeaturesTremont = FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; +constexpr FeatureBitset FeaturesAlderlake = + FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C | + FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU | + FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ | + FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG | + FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL; // Geode Processor. constexpr FeatureBitset FeaturesGeode = diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index c492d68..60c89b1 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -784,17 +784,6 @@ def ProcessorFeatures { list SPRFeatures = !listconcat(ICXFeatures, SPRAdditionalFeatures); - // Alderlake - list ADLAdditionalFeatures = [FeatureAVXVNNI, - FeatureCLDEMOTE, - FeatureHRESET, - FeaturePTWRITE, - FeatureSERIALIZE, - FeatureWAITPKG]; - list ADLTuning = SKLTuning; - list ADLFeatures = - !listconcat(SKLFeatures, ADLAdditionalFeatures); - // Atom list AtomFeatures = [FeatureX87, FeatureCMPXCHG8B, @@ -873,6 +862,31 @@ def ProcessorFeatures { list TRMFeatures = !listconcat(GLPFeatures, TRMAdditionalFeatures); + // Alderlake + list ADLAdditionalFeatures = [FeatureSERIALIZE, + FeaturePCONFIG, + FeatureSHSTK, + FeatureWIDEKL, + FeatureINVPCID, + FeatureADX, + FeatureFMA, + FeatureVAES, + FeatureVPCLMULQDQ, + FeatureF16C, + FeatureBMI, + FeatureBMI2, + FeatureLZCNT, + FeatureAVXVNNI, + FeaturePKU, + FeatureHRESET, + FeatureCLDEMOTE, + FeatureMOVDIRI, + FeatureMOVDIR64B, + FeatureWAITPKG]; + list ADLTuning = SKLTuning; + list ADLFeatures = + !listconcat(TRMFeatures, ADLAdditionalFeatures); + // Knights Landing list KNLFeatures = [FeatureX87, FeatureCMPXCHG8B, -- 2.7.4