From 5f69e53e5592141bf81f41fdf92106bf5cc3821c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 17 Apr 2020 13:37:47 -0700 Subject: [PATCH] [X86] Remove single incoming value phis from tests for the loop SAD pattern. NFC InstCombine should ensure these don't exist. I'm looking at making some changes to how we detect these patterns and not having to worry about these phis will help. --- llvm/test/CodeGen/X86/min-legal-vector-width.ll | 10 ++++------ llvm/test/CodeGen/X86/sad.ll | 20 ++++++++------------ 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/llvm/test/CodeGen/X86/min-legal-vector-width.ll b/llvm/test/CodeGen/X86/min-legal-vector-width.ll index 81de0ee..443d57a 100644 --- a/llvm/test/CodeGen/X86/min-legal-vector-width.ll +++ b/llvm/test/CodeGen/X86/min-legal-vector-width.ll @@ -358,9 +358,8 @@ vector.body: br i1 %11, label %middle.block, label %vector.body middle.block: - %.lcssa = phi <16 x i32> [ %10, %vector.body ] - %rdx.shuf = shufflevector <16 x i32> %.lcssa, <16 x i32> undef, <16 x i32> - %bin.rdx = add <16 x i32> %.lcssa, %rdx.shuf + %rdx.shuf = shufflevector <16 x i32> %10, <16 x i32> undef, <16 x i32> + %bin.rdx = add <16 x i32> %10, %rdx.shuf %rdx.shuf2 = shufflevector <16 x i32> %bin.rdx, <16 x i32> undef, <16 x i32> %bin.rdx2 = add <16 x i32> %bin.rdx, %rdx.shuf2 %rdx.shuf3 = shufflevector <16 x i32> %bin.rdx2, <16 x i32> undef, <16 x i32> @@ -420,9 +419,8 @@ vector.body: br i1 %11, label %middle.block, label %vector.body middle.block: - %.lcssa = phi <16 x i32> [ %10, %vector.body ] - %rdx.shuf = shufflevector <16 x i32> %.lcssa, <16 x i32> undef, <16 x i32> - %bin.rdx = add <16 x i32> %.lcssa, %rdx.shuf + %rdx.shuf = shufflevector <16 x i32> %10, <16 x i32> undef, <16 x i32> + %bin.rdx = add <16 x i32> %10, %rdx.shuf %rdx.shuf2 = shufflevector <16 x i32> %bin.rdx, <16 x i32> undef, <16 x i32> %bin.rdx2 = add <16 x i32> %bin.rdx, %rdx.shuf2 %rdx.shuf3 = shufflevector <16 x i32> %bin.rdx2, <16 x i32> undef, <16 x i32> diff --git a/llvm/test/CodeGen/X86/sad.ll b/llvm/test/CodeGen/X86/sad.ll index 6a74206..011f1db 100644 --- a/llvm/test/CodeGen/X86/sad.ll +++ b/llvm/test/CodeGen/X86/sad.ll @@ -135,9 +135,8 @@ vector.body: br i1 %11, label %middle.block, label %vector.body middle.block: - %.lcssa = phi <16 x i32> [ %10, %vector.body ] - %rdx.shuf = shufflevector <16 x i32> %.lcssa, <16 x i32> undef, <16 x i32> - %bin.rdx = add <16 x i32> %.lcssa, %rdx.shuf + %rdx.shuf = shufflevector <16 x i32> %10, <16 x i32> undef, <16 x i32> + %bin.rdx = add <16 x i32> %10, %rdx.shuf %rdx.shuf2 = shufflevector <16 x i32> %bin.rdx, <16 x i32> undef, <16 x i32> %bin.rdx2 = add <16 x i32> %bin.rdx, %rdx.shuf2 %rdx.shuf3 = shufflevector <16 x i32> %bin.rdx2, <16 x i32> undef, <16 x i32> @@ -293,9 +292,8 @@ vector.body: br i1 %11, label %middle.block, label %vector.body middle.block: - %.lcssa = phi <32 x i32> [ %10, %vector.body ] - %rdx.shuf = shufflevector <32 x i32> %.lcssa, <32 x i32> undef, <32 x i32> - %bin.rdx = add <32 x i32> %.lcssa, %rdx.shuf + %rdx.shuf = shufflevector <32 x i32> %10, <32 x i32> undef, <32 x i32> + %bin.rdx = add <32 x i32> %10, %rdx.shuf %rdx.shuf2 = shufflevector <32 x i32> %bin.rdx, <32 x i32> undef, <32 x i32> %bin.rdx2 = add <32 x i32> %bin.rdx, %rdx.shuf2 %rdx.shuf3 = shufflevector <32 x i32> %bin.rdx2, <32 x i32> undef, <32 x i32> @@ -525,9 +523,8 @@ vector.body: br i1 %11, label %middle.block, label %vector.body middle.block: - %.lcssa = phi <64 x i32> [ %10, %vector.body ] - %rdx.shuf = shufflevector <64 x i32> %.lcssa, <64 x i32> undef, <64 x i32> - %bin.rdx = add <64 x i32> %.lcssa, %rdx.shuf + %rdx.shuf = shufflevector <64 x i32> %10, <64 x i32> undef, <64 x i32> + %bin.rdx = add <64 x i32> %10, %rdx.shuf %rdx.shuf2 = shufflevector <64 x i32> %bin.rdx, <64 x i32> undef, <64 x i32> %bin.rdx2 = add <64 x i32> %bin.rdx, %rdx.shuf2 %rdx.shuf3 = shufflevector <64 x i32> %bin.rdx2, <64 x i32> undef, <64 x i32> @@ -611,9 +608,8 @@ vector.body: br i1 %11, label %middle.block, label %vector.body middle.block: - %.lcssa = phi <2 x i32> [ %10, %vector.body ] - %rdx.shuf = shufflevector <2 x i32> %.lcssa, <2 x i32> undef, <2 x i32> - %bin.rdx = add <2 x i32> %.lcssa, %rdx.shuf + %rdx.shuf = shufflevector <2 x i32> %10, <2 x i32> undef, <2 x i32> + %bin.rdx = add <2 x i32> %10, %rdx.shuf %12 = extractelement <2 x i32> %bin.rdx, i32 0 ret i32 %12 } -- 2.7.4