From 5f1b8181ad499108ecdfaa1fcac3d8326e2ef86d Mon Sep 17 00:00:00 2001 From: Konstantin Zhuravlyov Date: Thu, 27 Sep 2018 20:49:00 +0000 Subject: [PATCH] AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9 llvm-svn: 343264 --- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 8 ++++++-- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 9 +++++++-- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 25 +++++++++++++++++++------ llvm/lib/Target/AMDGPU/VOPInstructions.td | 22 +++++++++++----------- 4 files changed, 43 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index af3699d..2e73a02 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1710,7 +1710,9 @@ class VOPProfile _ArgVT> { field bit HasSDWAOMod = isFloatType.ret; field bit HasExt = getHasExt.ret; - field bit HasSDWA9 = HasExt; + field bit HasExtDPP = HasExt; + field bit HasExtSDWA = HasExt; + field bit HasExtSDWA9 = HasExt; field int NeedPatGen = PatGenMode.NoPattern; field Operand Src0PackedMod = !if(HasSrc0FloatMods, PackedF16InputMods, PackedI16InputMods); @@ -1761,7 +1763,9 @@ class VOPProfile _ArgVT> { class VOP_NO_EXT : VOPProfile { let HasExt = 0; - let HasSDWA9 = 0; + let HasExtDPP = 0; + let HasExtSDWA = 0; + let HasExtSDWA9 = 0; } class VOP_PAT_GEN : VOPProfile { diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 4c7a922..9f4673c 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -242,7 +242,9 @@ def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> { let Src0RC64 = VRegSrc_32; let HasExt = 0; - let HasSDWA9 = 0; + let HasExtDPP = 0; + let HasExtSDWA = 0; + let HasExtSDWA9 = 0; } // Special case because there are no true output operands. Hack vdst @@ -271,7 +273,10 @@ def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> { let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret; let HasExt = 0; - let HasSDWA9 = 0; + let HasExtDPP = 0; + let HasExtSDWA = 0; + let HasExtSDWA9 = 0; + let HasDst = 0; let EmitDst = 1; // force vdst emission } diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index be1b5c9..e9d12ba 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -252,8 +252,11 @@ class VOP_MAC : VOPProfile <[vt, vt, vt, vt]> { let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt>.ret; let HasSrc2 = 0; let HasSrc2Mods = 0; + let HasExt = 1; - let HasSDWA9 = 0; + let HasExtDPP = 1; + let HasExtSDWA = 1; + let HasExtSDWA9 = 0; } def VOP_MAC_F16 : VOP_MAC ; @@ -303,7 +306,9 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); let HasExt = 1; - let HasSDWA9 = 1; + let HasExtDPP = 1; + let HasExtSDWA = 1; + let HasExtSDWA9 = 1; } // Read in from vcc or arbitrary SGPR @@ -334,7 +339,9 @@ def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); let HasExt = 1; - let HasSDWA9 = 1; + let HasExtDPP = 1; + let HasExtSDWA = 1; + let HasExtSDWA9 = 1; } def VOP_READLANE : VOPProfile<[i32, i32, i32]> { @@ -344,8 +351,11 @@ def VOP_READLANE : VOPProfile<[i32, i32, i32]> { let Ins64 = Ins32; let Asm32 = " $vdst, $src0, $src1"; let Asm64 = Asm32; + let HasExt = 0; - let HasSDWA9 = 0; + let HasExtDPP = 0; + let HasExtSDWA = 0; + let HasExtSDWA9 = 0; } def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { @@ -355,10 +365,13 @@ def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { let Ins64 = Ins32; let Asm32 = " $vdst, $src0, $src1"; let Asm64 = Asm32; - let HasExt = 0; - let HasSDWA9 = 0; let HasSrc2 = 0; let HasSrc2Mods = 0; + + let HasExt = 0; + let HasExtDPP = 0; + let HasExtSDWA = 0; + let HasExtSDWA9 = 0; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index 76b9180..755e030 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -420,10 +420,10 @@ class VOP_SDWA_Pseudo pattern=[]> : let SDWA = 1; let Uses = [EXEC]; - let SubtargetPredicate = !if(P.HasExt, HasSDWA, DisableInst); - let AssemblerPredicate = !if(P.HasExt, HasSDWA, DisableInst); - let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.SDWA, - AMDGPUAsmVariants.Disable); + let SubtargetPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst); + let AssemblerPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst); + let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, + AMDGPUAsmVariants.Disable); let DecoderNamespace = "SDWA"; VOPProfile Pfl = P; @@ -471,10 +471,10 @@ class VOP_SDWA9_Real : let Constraints = ps.Constraints; let DisableEncoding = ps.DisableEncoding; - let SubtargetPredicate = !if(ps.Pfl.HasSDWA9, HasSDWA9, DisableInst); - let AssemblerPredicate = !if(ps.Pfl.HasSDWA9, HasSDWA9, DisableInst); - let AsmVariantName = !if(ps.Pfl.HasSDWA9, AMDGPUAsmVariants.SDWA9, - AMDGPUAsmVariants.Disable); + let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst); + let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst); + let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, + AMDGPUAsmVariants.Disable); let DecoderNamespace = "SDWA9"; // Copy relevant pseudo op flags @@ -520,9 +520,9 @@ class VOP_DPP : let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", ""); let SubtargetPredicate = HasDPP; - let AssemblerPredicate = !if(P.HasExt, HasDPP, DisableInst); - let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP, - AMDGPUAsmVariants.Disable); + let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst); + let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, + AMDGPUAsmVariants.Disable); let Constraints = !if(P.NumSrcArgs, "$old = $vdst", ""); let DisableEncoding = !if(P.NumSrcArgs, "$old", ""); let DecoderNamespace = "DPP"; -- 2.7.4