From 5f0b2976cb2b62668a076f54419c24b8ab677167 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Mon, 14 Apr 2008 16:08:25 -0700 Subject: [PATCH] x86: add pci=check_enable_amd_mmconf and dmi check so will disable that feature by default, and only enable that via pci=check_enable_amd_mmconf or for system match with dmi table. Signed-off-by: Yinghai Lu Signed-off-by: Ingo Molnar Signed-off-by: Thomas Gleixner --- arch/x86/kernel/mmconf-fam10h_64.c | 28 ++++++++++++++++++++++++++++ arch/x86/kernel/setup_64.c | 23 +++++++++++++++-------- arch/x86/pci/common.c | 4 ++++ arch/x86/pci/mmconfig-shared.c | 3 +++ arch/x86/pci/pci.h | 1 + 5 files changed, 51 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/mmconf-fam10h_64.c b/arch/x86/kernel/mmconf-fam10h_64.c index 3789792..edc5fbf 100644 --- a/arch/x86/kernel/mmconf-fam10h_64.c +++ b/arch/x86/kernel/mmconf-fam10h_64.c @@ -6,12 +6,15 @@ #include #include #include +#include #include #include #include #include #include +#include "../pci/pci.h" + struct pci_hostbridge_probe { u32 bus; u32 slot; @@ -176,6 +179,9 @@ void __cpuinit fam10h_check_enable_mmcfg(void) u64 val; u32 address; + if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) + return; + address = MSR_FAM10H_MMIO_CONF_BASE; rdmsrl(address, val); @@ -213,3 +219,25 @@ void __cpuinit fam10h_check_enable_mmcfg(void) FAM10H_MMIO_CONF_ENABLE; wrmsrl(address, val); } + +static int __devinit set_check_enable_amd_mmconf(const struct dmi_system_id *d) +{ + pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF; + return 0; +} + +static struct dmi_system_id __devinitdata mmconf_dmi_table[] = { + { + .callback = set_check_enable_amd_mmconf, + .ident = "Sun Microsystems Machine", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"), + }, + }, + {} +}; + +void __init check_enable_amd_mmconf_dmi(void) +{ + dmi_check_system(mmconf_dmi_table); +} diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c index d8a9ee7..2f5c488 100644 --- a/arch/x86/kernel/setup_64.c +++ b/arch/x86/kernel/setup_64.c @@ -289,6 +289,18 @@ static void __init parse_setup_data(void) } } +#ifdef CONFIG_PCI_MMCONFIG +extern void __cpuinit fam10h_check_enable_mmcfg(void); +extern void __init check_enable_amd_mmconf_dmi(void); +#else +void __cpuinit fam10h_check_enable_mmcfg(void) +{ +} +void __init check_enable_amd_mmconf_dmi(void) +{ +} +#endif + /* * setup_arch - architecture-specific boot-time initializations * @@ -510,6 +522,9 @@ void __init setup_arch(char **cmdline_p) conswitchp = &dummy_con; #endif #endif + + /* do this before identify_cpu for boot cpu */ + check_enable_amd_mmconf_dmi(); } static int __cpuinit get_model_name(struct cpuinfo_x86 *c) @@ -697,14 +712,6 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); } -#ifdef CONFIG_PCI_MMCONFIG -extern void __cpuinit fam10h_check_enable_mmcfg(void); -#else -void __cpuinit fam10h_check_enable_mmcfg(void) -{ -} -#endif - static void __cpuinit init_amd(struct cpuinfo_x86 *c) { unsigned level; diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 07d5318..2a4d751 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -425,6 +425,10 @@ char * __devinit pcibios_setup(char *str) pci_probe &= ~PCI_PROBE_MMCONF; return NULL; } + else if (!strcmp(str, "check_enable_amd_mmconf")) { + pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF; + return NULL; + } #endif else if (!strcmp(str, "noacpi")) { acpi_noirq_set(); diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index bdf6224..0cfebec 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -107,6 +107,9 @@ static const char __init *pci_mmcfg_amd_fam10h(void) int i; unsigned segnbits = 0, busnbits; + if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) + return NULL; + address = MSR_FAM10H_MMIO_CONF_BASE; if (rdmsr_safe(address, &low, &high)) return NULL; diff --git a/arch/x86/pci/pci.h b/arch/x86/pci/pci.h index c8b89a8..8ef86b5 100644 --- a/arch/x86/pci/pci.h +++ b/arch/x86/pci/pci.h @@ -26,6 +26,7 @@ #define PCI_ASSIGN_ALL_BUSSES 0x4000 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 #define PCI_USE__CRS 0x10000 +#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 extern unsigned int pci_probe; extern unsigned long pirq_table_addr; -- 2.7.4