From 5e97940cd27961a0b872ff551fc98135507288b3 Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Mon, 17 Feb 2020 17:06:05 +0000 Subject: [PATCH] [ARM,MVE] Add the vmovlbq,vmovltq intrinsic family. Summary: These intrinsics take a vector of 2n elements, and return a vector of n wider elements obtained by sign- or zero-extending every other element of the input vector. They're represented in IR as a shufflevector that extracts the odd or even elements of the input, followed by a sext or zext. Existing LLVM codegen already matches this pattern and generates the VMOVLB instruction (which widens the even-index input lanes). But no existing isel rule was generating VMOVLT, so I've added some. However, the new rules currently only work in little-endian MVE, because the pattern they expect from isel lowering includes a bitconvert which doesn't have the right semantics in big-endian. The output of one existing codegen test is improved by those new rules. This commit adds the unpredicated forms only. Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74336 --- clang/include/clang/Basic/arm_mve.td | 7 ++ clang/include/clang/Basic/arm_mve_defs.td | 3 + clang/lib/CodeGen/CGBuiltin.cpp | 11 ++ clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | 126 +++++++++++++++++++ llvm/lib/Target/ARM/ARMInstrMVE.td | 10 ++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vmovl.ll | 147 +++++++++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-shuffleext.ll | 12 +- 7 files changed, 308 insertions(+), 8 deletions(-) create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vmovl.c create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vmovl.ll diff --git a/clang/include/clang/Basic/arm_mve.td b/clang/include/clang/Basic/arm_mve.td index 21801b4..55ddfc2 100644 --- a/clang/include/clang/Basic/arm_mve.td +++ b/clang/include/clang/Basic/arm_mve.td @@ -420,6 +420,13 @@ defm : float_int_conversions; defm : float_int_conversions; defm : float_int_conversions; +let params = [s8, u8, s16, u16] in { + def vmovlbq: Intrinsic; + def vmovltq: Intrinsic; +} + let params = T.Float in { def vrndq: Intrinsic $a)>; diff --git a/clang/include/clang/Basic/arm_mve_defs.td b/clang/include/clang/Basic/arm_mve_defs.td index 9e5b7b3..f6816cd 100644 --- a/clang/include/clang/Basic/arm_mve_defs.td +++ b/clang/include/clang/Basic/arm_mve_defs.td @@ -128,6 +128,9 @@ def fptoui: IRBuilder<"CreateFPToUI">; def vrev: CGHelperFn<"ARMMVEVectorElementReverse"> { let special_params = [IRBuilderIntParam<1, "unsigned">]; } +def unzip: CGHelperFn<"VectorUnzip"> { + let special_params = [IRBuilderIntParam<1, "bool">]; +} // Helper for making boolean flags in IR def i1: IRBuilderBase { diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 788f14b..b30a79a0 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -7056,6 +7056,17 @@ static llvm::Value *ARMMVEVectorReinterpret(CGBuilderTy &Builder, } } +static llvm::Value *VectorUnzip(CGBuilderTy &Builder, llvm::Value *V, bool Odd) { + // Make a shufflevector that extracts every other element of a vector (evens + // or odds, as desired). + SmallVector Indices; + unsigned InputElements = V->getType()->getVectorNumElements(); + for (unsigned i = 0; i < InputElements; i += 2) + Indices.push_back(i + Odd); + return Builder.CreateShuffleVector(V, llvm::UndefValue::get(V->getType()), + Indices); +} + template static llvm::Value *ARMMVEConstantSplat(CGBuilderTy &Builder, llvm::Type *VT) { // MVE-specific helper function to make a vector splat of a constant such as diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c b/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c new file mode 100644 index 0000000..0b8ef59 --- /dev/null +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c @@ -0,0 +1,126 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s + +#include + +// CHECK-LABEL: @test_vmovlbq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <16 x i8> [[A:%.*]], <16 x i8> undef, <8 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i8> [[TMP0]] to <8 x i16> +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_vmovlbq_s8(int8x16_t a) +{ +#ifdef POLYMORPHIC + return vmovlbq(a); +#else /* POLYMORPHIC */ + return vmovlbq_s8(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmovlbq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> undef, <4 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_vmovlbq_s16(int16x8_t a) +{ +#ifdef POLYMORPHIC + return vmovlbq(a); +#else /* POLYMORPHIC */ + return vmovlbq_s16(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmovlbq_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <16 x i8> [[A:%.*]], <16 x i8> undef, <8 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = zext <8 x i8> [[TMP0]] to <8 x i16> +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_vmovlbq_u8(uint8x16_t a) +{ +#ifdef POLYMORPHIC + return vmovlbq(a); +#else /* POLYMORPHIC */ + return vmovlbq_u8(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmovlbq_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> undef, <4 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i16> [[TMP0]] to <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_vmovlbq_u16(uint16x8_t a) +{ +#ifdef POLYMORPHIC + return vmovlbq(a); +#else /* POLYMORPHIC */ + return vmovlbq_u16(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmovltq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <16 x i8> [[A:%.*]], <16 x i8> undef, <8 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i8> [[TMP0]] to <8 x i16> +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_vmovltq_s8(int8x16_t a) +{ +#ifdef POLYMORPHIC + return vmovltq(a); +#else /* POLYMORPHIC */ + return vmovltq_s8(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmovltq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> undef, <4 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_vmovltq_s16(int16x8_t a) +{ +#ifdef POLYMORPHIC + return vmovltq(a); +#else /* POLYMORPHIC */ + return vmovltq_s16(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmovltq_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <16 x i8> [[A:%.*]], <16 x i8> undef, <8 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = zext <8 x i8> [[TMP0]] to <8 x i16> +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_vmovltq_u8(uint8x16_t a) +{ +#ifdef POLYMORPHIC + return vmovltq(a); +#else /* POLYMORPHIC */ + return vmovltq_u8(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vmovltq_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> undef, <4 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i16> [[TMP0]] to <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_vmovltq_u16(uint16x8_t a) +{ +#ifdef POLYMORPHIC + return vmovltq(a); +#else /* POLYMORPHIC */ + return vmovltq_u16(a); +#endif /* POLYMORPHIC */ +} + diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index fffd86e..538a120 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -2394,6 +2394,16 @@ let Predicates = [HasMVEInt] in { def : Pat<(sext_inreg (v4i32 MQPR:$src), v4i8), (MVE_VMOVLs16bh (MVE_VMOVLs8bh MQPR:$src))>; + def : Pat<(sext_inreg (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src)))), + v8i8), (MVE_VMOVLs8th MQPR:$src)>; + def : Pat<(sext_inreg (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src)))), + v4i16), (MVE_VMOVLs16th MQPR:$src)>; + def : Pat<(ARMvbicImm (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src)))), + (i32 0xAFF)), (MVE_VMOVLu8th MQPR:$src)>; + def : Pat<(and (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src)))), + (v4i32 (ARMvmovImm (i32 0xCFF)))), + (MVE_VMOVLu16th MQPR:$src)>; + // zext_inreg 16 -> 32 def : Pat<(and (v4i32 MQPR:$src), (v4i32 (ARMvmovImm (i32 0xCFF)))), (MVE_VMOVLu16bh MQPR:$src)>; diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmovl.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmovl.ll new file mode 100644 index 0000000..c9ce38f --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmovl.ll @@ -0,0 +1,147 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=LE %s +; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=BE %s + +define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> %a) { +; LE-LABEL: test_vmovlbq_s8: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlb.s8 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovlbq_s8: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.8 q1, q0 +; BE-NEXT: vmovlb.s8 q1, q1 +; BE-NEXT: vrev64.16 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> + %1 = sext <8 x i8> %0 to <8 x i16> + ret <8 x i16> %1 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> %a) { +; LE-LABEL: test_vmovlbq_s16: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlb.s16 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovlbq_s16: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.16 q1, q0 +; BE-NEXT: vmovlb.s16 q1, q1 +; BE-NEXT: vrev64.32 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> + %1 = sext <4 x i16> %0 to <4 x i32> + ret <4 x i32> %1 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> %a) { +; LE-LABEL: test_vmovlbq_u8: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlb.u8 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovlbq_u8: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.8 q1, q0 +; BE-NEXT: vmovlb.u8 q1, q1 +; BE-NEXT: vrev64.16 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> + %1 = zext <8 x i8> %0 to <8 x i16> + ret <8 x i16> %1 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> %a) { +; LE-LABEL: test_vmovlbq_u16: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlb.u16 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovlbq_u16: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.16 q1, q0 +; BE-NEXT: vmovlb.u16 q1, q1 +; BE-NEXT: vrev64.32 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> + %1 = zext <4 x i16> %0 to <4 x i32> + ret <4 x i32> %1 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> %a) { +; LE-LABEL: test_vmovltq_s8: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlt.s8 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovltq_s8: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.8 q1, q0 +; BE-NEXT: vmovlt.s8 q1, q1 +; BE-NEXT: vrev64.16 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> + %1 = sext <8 x i8> %0 to <8 x i16> + ret <8 x i16> %1 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> %a) { +; LE-LABEL: test_vmovltq_s16: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlt.s16 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovltq_s16: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.16 q1, q0 +; BE-NEXT: vmovlt.s16 q1, q1 +; BE-NEXT: vrev64.32 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> + %1 = sext <4 x i16> %0 to <4 x i32> + ret <4 x i32> %1 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> %a) { +; LE-LABEL: test_vmovltq_u8: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlt.u8 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovltq_u8: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.8 q1, q0 +; BE-NEXT: vmovlt.u8 q1, q1 +; BE-NEXT: vrev64.16 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> + %1 = zext <8 x i8> %0 to <8 x i16> + ret <8 x i16> %1 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> %a) { +; LE-LABEL: test_vmovltq_u16: +; LE: @ %bb.0: @ %entry +; LE-NEXT: vmovlt.u16 q0, q0 +; LE-NEXT: bx lr +; +; BE-LABEL: test_vmovltq_u16: +; BE: @ %bb.0: @ %entry +; BE-NEXT: vrev64.16 q1, q0 +; BE-NEXT: vmovlt.u16 q1, q1 +; BE-NEXT: vrev64.32 q0, q1 +; BE-NEXT: bx lr +entry: + %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> + %1 = zext <4 x i16> %0 to <4 x i32> + ret <4 x i32> %1 +} diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll b/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll index 74596ff..bd4cf69 100644 --- a/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll +++ b/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll @@ -15,8 +15,7 @@ entry: define arm_aapcs_vfpcc <4 x i32> @sext_1357(<8 x i16> %src) { ; CHECK-LABEL: sext_1357: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vrev32.16 q0, q0 -; CHECK-NEXT: vmovlb.s16 q0, q0 +; CHECK-NEXT: vmovlt.s16 q0, q0 ; CHECK-NEXT: bx lr entry: %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> @@ -38,8 +37,7 @@ entry: define arm_aapcs_vfpcc <4 x i32> @zext_1357(<8 x i16> %src) { ; CHECK-LABEL: zext_1357: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vrev32.16 q0, q0 -; CHECK-NEXT: vmovlb.u16 q0, q0 +; CHECK-NEXT: vmovlt.u16 q0, q0 ; CHECK-NEXT: bx lr entry: %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> @@ -61,8 +59,7 @@ entry: define arm_aapcs_vfpcc <8 x i16> @sext_13579111315(<16 x i8> %src) { ; CHECK-LABEL: sext_13579111315: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vrev16.8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q0, q0 +; CHECK-NEXT: vmovlt.s8 q0, q0 ; CHECK-NEXT: bx lr entry: %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> @@ -84,8 +81,7 @@ entry: define arm_aapcs_vfpcc <8 x i16> @zext_13579111315(<16 x i8> %src) { ; CHECK-LABEL: zext_13579111315: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vrev16.8 q0, q0 -; CHECK-NEXT: vmovlb.u8 q0, q0 +; CHECK-NEXT: vmovlt.u8 q0, q0 ; CHECK-NEXT: bx lr entry: %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> -- 2.7.4