From 5e96cea1db0623a833d5376c9ea2ce4528771f97 Mon Sep 17 00:00:00 2001 From: Joe Loser Date: Tue, 6 Sep 2022 18:06:58 -0600 Subject: [PATCH] [llvm] Use std::size instead of llvm::array_lengthof LLVM contains a helpful function for getting the size of a C-style array: `llvm::array_lengthof`. This is useful prior to C++17, but not as helpful for C++17 or later: `std::size` already has support for C-style arrays. Change call sites to use `std::size` instead. Differential Revision: https://reviews.llvm.org/D133429 --- llvm/include/llvm/CodeGen/TargetLowering.h | 25 +++++++++++----------- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 8 +++---- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 14 ++++++------ llvm/lib/CodeGen/TargetLoweringBase.cpp | 2 +- llvm/lib/DWP/DWP.cpp | 2 +- llvm/lib/IR/DebugInfoMetadata.cpp | 7 +++--- llvm/lib/MC/MCAsmBackend.cpp | 2 +- llvm/lib/MC/MCDwarf.cpp | 2 +- llvm/lib/Object/MachOObjectFile.cpp | 2 +- llvm/lib/Support/ARMAttributeParser.cpp | 4 ++-- llvm/lib/Support/CrashRecoveryContext.cpp | 2 +- llvm/lib/Support/NativeFormatting.cpp | 2 +- llvm/lib/Support/Triple.cpp | 10 ++++----- llvm/lib/Support/Unix/Signals.inc | 10 ++++----- llvm/lib/Support/Windows/Path.inc | 2 +- llvm/lib/Support/Windows/Signals.inc | 2 +- llvm/lib/Support/X86TargetParser.cpp | 14 ++++++------ llvm/lib/Support/raw_ostream.cpp | 5 ++--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 ++-- llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp | 4 ++-- llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp | 2 +- llvm/lib/Target/ARC/ARCISelLowering.cpp | 11 +++++----- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 2 +- llvm/lib/Target/AVR/AVRISelLowering.cpp | 20 ++++++++--------- .../Hexagon/Disassembler/HexagonDisassembler.cpp | 8 +++---- llvm/lib/Target/Hexagon/HexagonFrameLowering.h | 2 +- llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 4 ++-- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 2 +- .../Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp | 2 +- .../lib/Target/LoongArch/LoongArchISelLowering.cpp | 4 ++-- .../LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp | 2 +- .../MSP430/MCTargetDesc/MSP430AsmBackend.cpp | 4 ++-- llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 4 ++-- .../Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | 4 ++-- llvm/lib/Target/Mips/Mips16ISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCCallingConv.cpp | 6 +++--- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 8 +++---- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 20 ++++++++--------- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 4 ++-- .../Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++-- .../Sparc/Disassembler/SparcDisassembler.cpp | 2 +- llvm/lib/Target/VE/VEFrameLowering.h | 2 +- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 4 ++-- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++-- llvm/lib/Target/XCore/XCoreISelLowering.cpp | 4 ++-- .../Transforms/InstCombine/InstCombineAddSub.cpp | 3 +-- llvm/lib/Transforms/Utils/MetaRenamer.cpp | 2 +- llvm/tools/llvm-objdump/COFFDump.cpp | 2 +- llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp | 4 ++-- llvm/tools/llvm-readobj/ELFDumper.cpp | 2 +- llvm/unittests/ADT/APFloatTest.cpp | 20 ++++++++--------- llvm/unittests/ADT/StringRefTest.cpp | 12 +++++------ llvm/unittests/ADT/TinyPtrVectorTest.cpp | 2 +- llvm/unittests/ProfileData/CoverageMappingTest.cpp | 4 ++-- llvm/unittests/Support/BinaryStreamTest.cpp | 2 +- llvm/unittests/Support/CSKYTargetParserTest.cpp | 2 +- llvm/unittests/Support/CommandLineTest.cpp | 14 ++++++------ llvm/unittests/Support/FormatVariadicTest.cpp | 3 +-- llvm/unittests/Support/TargetParserTest.cpp | 12 +++++------ llvm/utils/KillTheDoctor/KillTheDoctor.cpp | 16 +++++--------- llvm/utils/TableGen/AsmWriterEmitter.cpp | 2 +- llvm/utils/TableGen/CodeGenTarget.cpp | 2 +- llvm/utils/TableGen/RegisterInfoEmitter.cpp | 4 ++-- llvm/utils/TableGen/X86DisassemblerTables.cpp | 2 +- 69 files changed, 182 insertions(+), 192 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 75d3fa6..82949f4 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -935,7 +935,7 @@ public: /// promotions or expansions. bool isTypeLegal(EVT VT) const { assert(!VT.isSimple() || - (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); + (unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT)); return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; } @@ -1110,7 +1110,8 @@ public: if (VT.isExtended()) return Expand; // If a target-specific SDNode requires legalization, require the target // to provide custom legalization for it. - if (Op >= array_lengthof(OpActions[0])) return Custom; + if (Op >= std::size(OpActions[0])) + return Custom; return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; } @@ -1417,8 +1418,8 @@ public: /// expander for it. LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const { - assert((unsigned)CC < array_lengthof(CondCodeActions) && - ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && + assert((unsigned)CC < std::size(CondCodeActions) && + ((unsigned)VT.SimpleTy >> 3) < std::size(CondCodeActions[0]) && "Table isn't big enough!"); // See setCondCodeAction for how this is encoded. uint32_t Shift = 4 * (VT.SimpleTy & 0x7); @@ -1526,7 +1527,7 @@ public: /// Return the type of registers that this ValueType will eventually require. MVT getRegisterType(MVT VT) const { - assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); + assert((unsigned)VT.SimpleTy < std::size(RegisterTypeForVT)); return RegisterTypeForVT[VT.SimpleTy]; } @@ -1534,7 +1535,7 @@ public: MVT getRegisterType(LLVMContext &Context, EVT VT) const { if (VT.isSimple()) { assert((unsigned)VT.getSimpleVT().SimpleTy < - array_lengthof(RegisterTypeForVT)); + std::size(RegisterTypeForVT)); return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; } if (VT.isVector()) { @@ -1567,7 +1568,7 @@ public: Optional RegisterVT = None) const { if (VT.isSimple()) { assert((unsigned)VT.getSimpleVT().SimpleTy < - array_lengthof(NumRegistersForVT)); + std::size(NumRegistersForVT)); return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; } if (VT.isVector()) { @@ -1635,7 +1636,7 @@ public: /// If true, the target has custom DAG combine transformations that it can /// perform for the specified node. bool hasTargetDAGCombine(ISD::NodeType NT) const { - assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); + assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray)); return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); } @@ -2298,7 +2299,7 @@ protected: /// specified value type. This indicates the selector can handle values of /// that class natively. void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { - assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); + assert((unsigned)VT.SimpleTy < std::size(RegClassForVT)); RegClassForVT[VT.SimpleTy] = RC; } @@ -2315,7 +2316,7 @@ protected: /// type and indicate what to do about it. Note that VT may refer to either /// the type of a result or that of an operand of Op. void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) { - assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); + assert(Op < std::size(OpActions[0]) && "Table isn't big enough!"); OpActions[(unsigned)VT.SimpleTy][Op] = Action; } void setOperationAction(ArrayRef Ops, MVT VT, @@ -2417,7 +2418,7 @@ protected: void setCondCodeAction(ArrayRef CCs, MVT VT, LegalizeAction Action) { for (auto CC : CCs) { - assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) && + assert(VT.isValid() && (unsigned)CC < std::size(CondCodeActions) && "Table isn't big enough!"); assert((unsigned)Action < 0x10 && "too many bits for bitfield array"); /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the @@ -2454,7 +2455,7 @@ protected: /// PerformDAGCombine virtual method. void setTargetDAGCombine(ArrayRef NTs) { for (auto NT : NTs) { - assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); + assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray)); TargetDAGCombineArray[NT >> 3] |= 1 << (NT & 7); } } diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 5179631..ef66104 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -4311,7 +4311,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( // The input vector this mask element indexes into. unsigned Input = (unsigned)Idx / NewElts; - if (Input >= array_lengthof(Inputs)) { + if (Input >= std::size(Inputs)) { // The mask element does not index into any input vector. Ops.push_back(-1); continue; @@ -4322,7 +4322,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( // Find or create a shuffle vector operand to hold this input. unsigned OpNo; - for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { + for (OpNo = 0; OpNo < std::size(InputUsed); ++OpNo) { if (InputUsed[OpNo] == Input) { // This input vector is already an operand. break; @@ -4333,7 +4333,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( } } - if (OpNo >= array_lengthof(InputUsed)) { + if (OpNo >= std::size(InputUsed)) { // More than two input vectors used! Give up on trying to create a // shuffle vector. Insert all elements into a BUILD_VECTOR instead. UseBuildVector = true; @@ -4356,7 +4356,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( // The input vector this mask element indexes into. unsigned Input = (unsigned)Idx / NewElts; - if (Input >= array_lengthof(Inputs)) { + if (Input >= std::size(Inputs)) { // The mask element is "undef" or indexes off the end of the input. SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); continue; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index f2a1586..b79e085 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -2378,7 +2378,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, &DL](SmallVectorImpl &Mask) { // Check if all inputs are shuffles of the same operands or non-shuffles. MapVector, SmallVector> ShufflesIdxs; - for (unsigned Idx = 0; Idx < array_lengthof(Inputs); ++Idx) { + for (unsigned Idx = 0; Idx < std::size(Inputs); ++Idx) { SDValue Input = Inputs[Idx]; auto *Shuffle = dyn_cast(Input.getNode()); if (!Shuffle || @@ -2425,7 +2425,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, ShufflesIdxs[std::make_pair(P.first.second, P.first.first)].clear(); } // Check if any concat_vectors can be simplified. - SmallBitVector UsedSubVector(2 * array_lengthof(Inputs)); + SmallBitVector UsedSubVector(2 * std::size(Inputs)); for (int &Idx : Mask) { if (Idx == UndefMaskElem) continue; @@ -2445,7 +2445,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, } if (UsedSubVector.count() > 1) { SmallVector, 2>> Pairs; - for (unsigned I = 0; I < array_lengthof(Inputs); ++I) { + for (unsigned I = 0; I < std::size(Inputs); ++I) { if (UsedSubVector.test(2 * I) == UsedSubVector.test(2 * I + 1)) continue; if (Pairs.empty() || Pairs.back().size() == 2) @@ -2489,7 +2489,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, // Try to remove extra shuffles (except broadcasts) and shuffles with the // reused operands. Changed = false; - for (unsigned I = 0; I < array_lengthof(Inputs); ++I) { + for (unsigned I = 0; I < std::size(Inputs); ++I) { auto *Shuffle = dyn_cast(Inputs[I].getNode()); if (!Shuffle) continue; @@ -2589,7 +2589,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, } // Adjust mask in case of reused inputs. Also, need to insert constant // inputs at first, otherwise it affects the final outcome. - if (UniqueInputs.size() != array_lengthof(Inputs)) { + if (UniqueInputs.size() != std::size(Inputs)) { auto &&UniqueVec = UniqueInputs.takeVector(); auto &&UniqueConstantVec = UniqueConstantInputs.takeVector(); unsigned ConstNum = UniqueConstantVec.size(); @@ -2627,7 +2627,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, // Build a shuffle mask for the output, discovering on the fly which // input vectors to use as shuffle operands. unsigned FirstMaskIdx = High * NewElts; - SmallVector Mask(NewElts * array_lengthof(Inputs), UndefMaskElem); + SmallVector Mask(NewElts * std::size(Inputs), UndefMaskElem); copy(makeArrayRef(OrigMask).slice(FirstMaskIdx, NewElts), Mask.begin()); assert(!Output && "Expected default initialized initial value."); TryPeekThroughShufflesInputs(Mask); @@ -2647,7 +2647,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, return SecondIteration; }; processShuffleMasks( - Mask, array_lengthof(Inputs), array_lengthof(Inputs), + Mask, std::size(Inputs), std::size(Inputs), /*NumOfUsedRegs=*/1, [&Output, &DAG = DAG, NewVT]() { Output = DAG.getUNDEF(NewVT); }, [&Output, &DAG = DAG, NewVT, &DL, &Inputs, diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 9bc2a1e..0994936 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -950,7 +950,7 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { // If this is a simple type, use the ComputeRegisterProp mechanism. if (VT.isSimple()) { MVT SVT = VT.getSimpleVT(); - assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); + assert((unsigned)SVT.SimpleTy < std::size(TransformToType)); MVT NVT = TransformToType[SVT.SimpleTy]; LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); diff --git a/llvm/lib/DWP/DWP.cpp b/llvm/lib/DWP/DWP.cpp index 7f825a1..425650a 100644 --- a/llvm/lib/DWP/DWP.cpp +++ b/llvm/lib/DWP/DWP.cpp @@ -407,7 +407,7 @@ void writeIndexTable( const MapVector &IndexEntries, uint32_t DWARFUnitIndex::Entry::SectionContribution::*Field) { for (const auto &E : IndexEntries) - for (size_t I = 0; I != array_lengthof(E.second.Contributions); ++I) + for (size_t I = 0; I != std::size(E.second.Contributions); ++I) if (ContributionOffsets[I]) Out.emitIntValue(E.second.Contributions[I].*Field, 4); } diff --git a/llvm/lib/IR/DebugInfoMetadata.cpp b/llvm/lib/IR/DebugInfoMetadata.cpp index 1b2c3ee..877618d 100644 --- a/llvm/lib/IR/DebugInfoMetadata.cpp +++ b/llvm/lib/IR/DebugInfoMetadata.cpp @@ -329,7 +329,7 @@ void GenericDINode::recalculateHash() { } \ } while (false) #define DEFINE_GETIMPL_STORE(CLASS, ARGS, OPS) \ - return storeImpl(new (array_lengthof(OPS), Storage) \ + return storeImpl(new (std::size(OPS), Storage) \ CLASS(Context, Storage, UNWRAP_ARGS(ARGS), OPS), \ Storage, Context.pImpl->CLASS##s) #define DEFINE_GETIMPL_STORE_NO_OPS(CLASS, ARGS) \ @@ -337,8 +337,7 @@ void GenericDINode::recalculateHash() { CLASS(Context, Storage, UNWRAP_ARGS(ARGS)), \ Storage, Context.pImpl->CLASS##s) #define DEFINE_GETIMPL_STORE_NO_CONSTRUCTOR_ARGS(CLASS, OPS) \ - return storeImpl(new (array_lengthof(OPS), Storage) \ - CLASS(Context, Storage, OPS), \ + return storeImpl(new (std::size(OPS), Storage) CLASS(Context, Storage, OPS), \ Storage, Context.pImpl->CLASS##s) #define DEFINE_GETIMPL_STORE_N(CLASS, ARGS, OPS, NUM_OPS) \ return storeImpl(new (NUM_OPS, Storage) \ @@ -850,7 +849,7 @@ DICompileUnit *DICompileUnit::getImpl( Macros, SysRoot, SDK}; - return storeImpl(new (array_lengthof(Ops), Storage) DICompileUnit( + return storeImpl(new (std::size(Ops), Storage) DICompileUnit( Context, Storage, SourceLanguage, IsOptimized, RuntimeVersion, EmissionKind, DWOId, SplitDebugInlining, DebugInfoForProfiling, NameTableKind, RangesBaseAddress, diff --git a/llvm/lib/MC/MCAsmBackend.cpp b/llvm/lib/MC/MCAsmBackend.cpp index 4ed9d85..3a23102 100644 --- a/llvm/lib/MC/MCAsmBackend.cpp +++ b/llvm/lib/MC/MCAsmBackend.cpp @@ -105,7 +105,7 @@ const MCFixupKindInfo &MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"FK_SecRel_8", 0, 64, 0}, }; - assert((size_t)Kind <= array_lengthof(Builtins) && "Unknown fixup kind"); + assert((size_t)Kind <= std::size(Builtins) && "Unknown fixup kind"); return Builtins[Kind]; } diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp index cc1a662..66d5d3c 100644 --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -306,7 +306,7 @@ MCDwarfLineTableHeader::Emit(MCStreamer *MCOS, MCDwarfLineTableParams Params, 0, // length of DW_LNS_set_epilogue_begin 1 // DW_LNS_set_isa }; - assert(array_lengthof(StandardOpcodeLengths) >= + assert(std::size(StandardOpcodeLengths) >= (Params.DWARF2LineOpcodeBase - 1U)); return Emit( MCOS, Params, diff --git a/llvm/lib/Object/MachOObjectFile.cpp b/llvm/lib/Object/MachOObjectFile.cpp index 0b06ec3..16a24d1 100644 --- a/llvm/lib/Object/MachOObjectFile.cpp +++ b/llvm/lib/Object/MachOObjectFile.cpp @@ -2329,7 +2329,7 @@ void MachOObjectFile::getRelocationTypeName( "ARM64_RELOC_ADDEND" }; - if (RType >= array_lengthof(Table)) + if (RType >= std::size(Table)) res = "Unknown"; else res = Table[RType]; diff --git a/llvm/lib/Support/ARMAttributeParser.cpp b/llvm/lib/Support/ARMAttributeParser.cpp index 5f79510..b76a803 100644 --- a/llvm/lib/Support/ARMAttributeParser.cpp +++ b/llvm/lib/Support/ARMAttributeParser.cpp @@ -214,7 +214,7 @@ Error ARMAttributeParser::ABI_align_needed(AttrType tag) { uint64_t value = de.getULEB128(cursor); std::string description; - if (value < array_lengthof(strings)) + if (value < std::size(strings)) description = strings[value]; else if (value <= 12) description = "8-byte alignment, " + utostr(1ULL << value) + @@ -233,7 +233,7 @@ Error ARMAttributeParser::ABI_align_preserved(AttrType tag) { uint64_t value = de.getULEB128(cursor); std::string description; - if (value < array_lengthof(strings)) + if (value < std::size(strings)) description = std::string(strings[value]); else if (value <= 12) description = std::string("8-byte stack alignment, ") + diff --git a/llvm/lib/Support/CrashRecoveryContext.cpp b/llvm/lib/Support/CrashRecoveryContext.cpp index ae58418..b2caaee 100644 --- a/llvm/lib/Support/CrashRecoveryContext.cpp +++ b/llvm/lib/Support/CrashRecoveryContext.cpp @@ -353,7 +353,7 @@ static void uninstallExceptionOrSignalHandlers() { static const int Signals[] = { SIGABRT, SIGBUS, SIGFPE, SIGILL, SIGSEGV, SIGTRAP }; -static const unsigned NumSignals = array_lengthof(Signals); +static const unsigned NumSignals = std::size(Signals); static struct sigaction PrevActions[NumSignals]; static void CrashRecoverySignalHandler(int Signal) { diff --git a/llvm/lib/Support/NativeFormatting.cpp b/llvm/lib/Support/NativeFormatting.cpp index 8a69f75..9cf7e20a 100644 --- a/llvm/lib/Support/NativeFormatting.cpp +++ b/llvm/lib/Support/NativeFormatting.cpp @@ -149,7 +149,7 @@ void llvm::write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style, std::max(static_cast(W), std::max(1u, Nibbles) + PrefixChars); char NumberBuffer[kMaxWidth]; - ::memset(NumberBuffer, '0', llvm::array_lengthof(NumberBuffer)); + ::memset(NumberBuffer, '0', std::size(NumberBuffer)); if (Prefix) NumberBuffer[1] = 'x'; char *EndPtr = NumberBuffer + NumChars; diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp index 33416fc..faf372f 100644 --- a/llvm/lib/Support/Triple.cpp +++ b/llvm/lib/Support/Triple.cpp @@ -982,13 +982,13 @@ std::string Triple::normalize(StringRef Str) { // If they are not there already, permute the components into their canonical // positions by seeing if they parse as a valid architecture, and if so moving // the component to the architecture position etc. - for (unsigned Pos = 0; Pos != array_lengthof(Found); ++Pos) { + for (unsigned Pos = 0; Pos != std::size(Found); ++Pos) { if (Found[Pos]) continue; // Already in the canonical position. for (unsigned Idx = 0; Idx != Components.size(); ++Idx) { // Do not reparse any components that already matched. - if (Idx < array_lengthof(Found) && Found[Idx]) + if (Idx < std::size(Found) && Found[Idx]) continue; // Does this component parse as valid for the target position? @@ -1036,7 +1036,7 @@ std::string Triple::normalize(StringRef Str) { // components to the right. for (unsigned i = Pos; !CurrentComponent.empty(); ++i) { // Skip over any fixed components. - while (i < array_lengthof(Found) && Found[i]) + while (i < std::size(Found) && Found[i]) ++i; // Place the component at the new position, getting the component // that was at this position - it will be moved right. @@ -1057,7 +1057,7 @@ std::string Triple::normalize(StringRef Str) { if (CurrentComponent.empty()) break; // Advance to the next component, skipping any fixed components. - while (++i < array_lengthof(Found) && Found[i]) + while (++i < std::size(Found) && Found[i]) ; } // The last component was pushed off the end - append it. @@ -1065,7 +1065,7 @@ std::string Triple::normalize(StringRef Str) { Components.push_back(CurrentComponent); // Advance Idx to the component's new position. - while (++Idx < array_lengthof(Found) && Found[Idx]) + while (++Idx < std::size(Found) && Found[Idx]) ; } while (Idx < Pos); // Add more until the final position is reached. } diff --git a/llvm/lib/Support/Unix/Signals.inc b/llvm/lib/Support/Unix/Signals.inc index bf145bf..3c34da8f 100644 --- a/llvm/lib/Support/Unix/Signals.inc +++ b/llvm/lib/Support/Unix/Signals.inc @@ -239,8 +239,8 @@ static const int InfoSigs[] = { }; static const size_t NumSigs = - array_lengthof(IntSigs) + array_lengthof(KillSigs) + - array_lengthof(InfoSigs) + 1 /* SIGPIPE */; + std::size(IntSigs) + std::size(KillSigs) + + std::size(InfoSigs) + 1 /* SIGPIPE */; static std::atomic NumRegisteredSignals = ATOMIC_VAR_INIT(0); @@ -298,7 +298,7 @@ static void RegisterHandlers() { // Not signal-safe. enum class SignalKind { IsKill, IsInfo }; auto registerHandler = [&](int Signal, SignalKind Kind) { unsigned Index = NumRegisteredSignals.load(); - assert(Index < array_lengthof(RegisteredSignalInfo) && + assert(Index < std::size(RegisteredSignalInfo) && "Out of space for signal handlers!"); struct sigaction NewHandler; @@ -566,13 +566,13 @@ void llvm::sys::PrintStackTrace(raw_ostream &OS, int Depth) { #if defined(HAVE_BACKTRACE) // Use backtrace() to output a backtrace on Linux systems with glibc. if (!depth) - depth = backtrace(StackTrace, static_cast(array_lengthof(StackTrace))); + depth = backtrace(StackTrace, static_cast(std::size(StackTrace))); #endif #if defined(HAVE__UNWIND_BACKTRACE) // Try _Unwind_Backtrace() if backtrace() failed. if (!depth) depth = unwindBacktrace(StackTrace, - static_cast(array_lengthof(StackTrace))); + static_cast(std::size(StackTrace))); #endif if (!depth) return; diff --git a/llvm/lib/Support/Windows/Path.inc b/llvm/lib/Support/Windows/Path.inc index 1e9788a..9101c1c 100644 --- a/llvm/lib/Support/Windows/Path.inc +++ b/llvm/lib/Support/Windows/Path.inc @@ -687,7 +687,7 @@ static bool isReservedName(StringRef path) { return true; // Then compare against the list of ancient reserved names. - for (size_t i = 0; i < array_lengthof(sReservedNames); ++i) { + for (size_t i = 0; i < std::size(sReservedNames); ++i) { if (path.equals_insensitive(sReservedNames[i])) return true; } diff --git a/llvm/lib/Support/Windows/Signals.inc b/llvm/lib/Support/Windows/Signals.inc index 1621f4a..aeb3707 100644 --- a/llvm/lib/Support/Windows/Signals.inc +++ b/llvm/lib/Support/Windows/Signals.inc @@ -246,7 +246,7 @@ static bool printStackTraceWithLLVMSymbolizer(llvm::raw_ostream &OS, if (StackFrame.AddrFrame.Offset == 0) break; StackTrace[Depth++] = (void *)(uintptr_t)StackFrame.AddrPC.Offset; - if (Depth >= array_lengthof(StackTrace)) + if (Depth >= std::size(StackTrace)) break; } diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index bb62102..1f72f58 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -54,7 +54,7 @@ public: } constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { + for (unsigned I = 0, E = std::size(Bits); I != E; ++I) { // GCC <6.2 crashes if this is written in a single statement. uint32_t NewBits = Bits[I] & RHS.Bits[I]; Bits[I] = NewBits; @@ -63,7 +63,7 @@ public: } constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) { + for (unsigned I = 0, E = std::size(Bits); I != E; ++I) { // GCC <6.2 crashes if this is written in a single statement. uint32_t NewBits = Bits[I] | RHS.Bits[I]; Bits[I] = NewBits; @@ -74,7 +74,7 @@ public: // gcc 5.3 miscompiles this if we try to write this using operator&=. constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { FeatureBitset Result; - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) + for (unsigned I = 0, E = std::size(Bits); I != E; ++I) Result.Bits[I] = Bits[I] & RHS.Bits[I]; return Result; } @@ -82,20 +82,20 @@ public: // gcc 5.3 miscompiles this if we try to write this using operator&=. constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { FeatureBitset Result; - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) + for (unsigned I = 0, E = std::size(Bits); I != E; ++I) Result.Bits[I] = Bits[I] | RHS.Bits[I]; return Result; } constexpr FeatureBitset operator~() const { FeatureBitset Result; - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) + for (unsigned I = 0, E = std::size(Bits); I != E; ++I) Result.Bits[I] = ~Bits[I]; return Result; } constexpr bool operator!=(const FeatureBitset &RHS) const { - for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) + for (unsigned I = 0, E = std::size(Bits); I != E; ++I) if (Bits[I] != RHS.Bits[I]) return true; return false; @@ -692,7 +692,7 @@ unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) { #include "llvm/Support/X86TargetParser.def" std::numeric_limits::max() // Need to consume last comma. }; - std::array HelperList; + std::array HelperList; std::iota(HelperList.begin(), HelperList.end(), 0); assert(std::is_permutation(HelperList.begin(), HelperList.end(), std::begin(Priorities), diff --git a/llvm/lib/Support/raw_ostream.cpp b/llvm/lib/Support/raw_ostream.cpp index 71d0b59..63cdc53 100644 --- a/llvm/lib/Support/raw_ostream.cpp +++ b/llvm/lib/Support/raw_ostream.cpp @@ -480,12 +480,11 @@ static raw_ostream &write_padding(raw_ostream &OS, unsigned NumChars) { C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C}; // Usually the indentation is small, handle it with a fastpath. - if (NumChars < array_lengthof(Chars)) + if (NumChars < std::size(Chars)) return OS.write(Chars, NumChars); while (NumChars) { - unsigned NumToWrite = std::min(NumChars, - (unsigned)array_lengthof(Chars)-1); + unsigned NumToWrite = std::min(NumChars, (unsigned)std::size(Chars) - 1); OS.write(Chars, NumToWrite); NumChars -= NumToWrite; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 67a5f88..e985d34 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -6203,7 +6203,7 @@ void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo, static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 }; - unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs); + unsigned NumGPRArgRegs = std::size(GPRArgRegs); if (Subtarget->isWindowsArm64EC()) { // In the ARM64EC ABI, only x0-x3 are used to pass arguments to varargs // functions. @@ -6256,7 +6256,7 @@ void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo, static const MCPhysReg FPRArgRegs[] = { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7}; - static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs); + static const unsigned NumFPRArgRegs = std::size(FPRArgRegs); unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs); unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp index aa7c7ff..1b0d7bb 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp @@ -347,7 +347,7 @@ const UnmangledFuncInfo UnmangledFuncInfo::Table[] = { }; const unsigned UnmangledFuncInfo::TableSize = - array_lengthof(UnmangledFuncInfo::Table); + std::size(UnmangledFuncInfo::Table); static AMDGPULibFunc::Param getRetType(AMDGPULibFunc::EFuncId id, const AMDGPULibFunc::Param (&Leads)[2]) { @@ -555,7 +555,7 @@ static AMDGPULibFunc::ENamePrefix parseNamePrefix(StringRef& mangledName) { } StringMap ManglingRule::buildManglingRulesMap() { - StringMap Map(array_lengthof(manglingRules)); + StringMap Map(std::size(manglingRules)); int Id = 0; for (auto Rule : manglingRules) Map.insert({Rule.Name, Id++}); diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp index c329bae..941f54c 100644 --- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp @@ -29,7 +29,7 @@ unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { R600::sub12, R600::sub13, R600::sub14, R600::sub15 }; - assert(Channel < array_lengthof(SubRegFromChannelTable)); + assert(Channel < std::size(SubRegFromChannelTable)); return SubRegFromChannelTable[Channel]; } diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp index 7fd08f7..2160d18 100644 --- a/llvm/lib/Target/ARC/ARCISelLowering.cpp +++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp @@ -560,18 +560,17 @@ SDValue ARCTargetLowering::LowerCallArguments( ARC::R4, ARC::R5, ARC::R6, ARC::R7}; auto *AFI = MF.getInfo(); unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); - if (FirstVAReg < array_lengthof(ArgRegs)) { + if (FirstVAReg < std::size(ArgRegs)) { int Offset = 0; // Save remaining registers, storing higher register numbers at a higher // address - // There are (array_lengthof(ArgRegs) - FirstVAReg) registers which + // There are (std::size(ArgRegs) - FirstVAReg) registers which // need to be saved. - int VarFI = - MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4, - CCInfo.getNextStackOffset(), true); + int VarFI = MFI.CreateFixedObject((std::size(ArgRegs) - FirstVAReg) * 4, + CCInfo.getNextStackOffset(), true); AFI->setVarArgsFrameIndex(VarFI); SDValue FIN = DAG.getFrameIndex(VarFI, MVT::i32); - for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) { + for (unsigned i = FirstVAReg; i < std::size(ArgRegs); i++) { // Move argument from phys reg -> virt reg unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); RegInfo.addLiveIn(ArgRegs[i], VReg); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 4142eeb..9f4025d 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -115,7 +115,7 @@ static const ARM_MLxEntry ARM_MLxTable[] = { ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), Subtarget(STI) { - for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { + for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) { if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) llvm_unreachable("Duplicated entries?"); MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index a0a2087..745e78b 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -2792,7 +2792,7 @@ bool ARMFrameLowering::assignCalleeSavedSpillSlots( const TargetFrameLowering::SpillSlot * ARMFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const { static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}}; - NumEntries = array_lengthof(FixedSpillOffsets); + NumEntries = std::size(FixedSpillOffsets); return FixedSpillOffsets; } diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index d6bd93f..350453d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4486,7 +4486,7 @@ SDValue ARMTargetLowering::LowerFormalArguments( int lastInsIndex = -1; if (isVarArg && MFI.hasVAStart()) { unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); - if (RegIdx != array_lengthof(GPRArgRegs)) + if (RegIdx != std::size(GPRArgRegs)) ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]); } diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index 3dddbb9..7acfb9b 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -245,7 +245,7 @@ INITIALIZE_PASS(Thumb2SizeReduce, DEBUG_TYPE, THUMB2_SIZE_REDUCE_NAME, false, Thumb2SizeReduce::Thumb2SizeReduce(std::function Ftor) : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) { OptimizeSize = MinimizeSize = false; - for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) { + for (unsigned i = 0, e = std::size(ReduceTable); i != e; ++i) { unsigned FromOpc = ReduceTable[i].WideOpc; if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second) llvm_unreachable("Duplicated entries?"); diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index 7de585e..8f7fa72 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -1108,9 +1108,9 @@ static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21, AVR::R21R20}; -static_assert(array_lengthof(RegList8AVR) == array_lengthof(RegList16AVR), +static_assert(std::size(RegList8AVR) == std::size(RegList16AVR), "8-bit and 16-bit register arrays must be of equal length"); -static_assert(array_lengthof(RegList8Tiny) == array_lengthof(RegList16Tiny), +static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny), "8-bit and 16-bit register arrays must be of equal length"); /// Analyze incoming and outgoing function arguments. We need custom C++ code @@ -1127,11 +1127,11 @@ static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, ArrayRef RegList8; ArrayRef RegList16; if (Tiny) { - RegList8 = makeArrayRef(RegList8Tiny, array_lengthof(RegList8Tiny)); - RegList16 = makeArrayRef(RegList16Tiny, array_lengthof(RegList16Tiny)); + RegList8 = makeArrayRef(RegList8Tiny, std::size(RegList8Tiny)); + RegList16 = makeArrayRef(RegList16Tiny, std::size(RegList16Tiny)); } else { - RegList8 = makeArrayRef(RegList8AVR, array_lengthof(RegList8AVR)); - RegList16 = makeArrayRef(RegList16AVR, array_lengthof(RegList16AVR)); + RegList8 = makeArrayRef(RegList8AVR, std::size(RegList8AVR)); + RegList16 = makeArrayRef(RegList16AVR, std::size(RegList16AVR)); } unsigned NumArgs = Args.size(); @@ -1223,11 +1223,11 @@ static void analyzeReturnValues(const SmallVectorImpl &Args, ArrayRef RegList8; ArrayRef RegList16; if (Tiny) { - RegList8 = makeArrayRef(RegList8Tiny, array_lengthof(RegList8Tiny)); - RegList16 = makeArrayRef(RegList16Tiny, array_lengthof(RegList16Tiny)); + RegList8 = makeArrayRef(RegList8Tiny, std::size(RegList8Tiny)); + RegList16 = makeArrayRef(RegList16Tiny, std::size(RegList16Tiny)); } else { - RegList8 = makeArrayRef(RegList8AVR, array_lengthof(RegList8AVR)); - RegList16 = makeArrayRef(RegList16AVR, array_lengthof(RegList16AVR)); + RegList8 = makeArrayRef(RegList8AVR, std::size(RegList8AVR)); + RegList16 = makeArrayRef(RegList16AVR, std::size(RegList16AVR)); } // GCC-ABI says that the size is rounded up to the next even number, diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 58d5df4..8792ce3 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -680,7 +680,7 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, /* 28 */ 0, 0, UTIMERLO, UTIMERHI }; - if (RegNo >= array_lengthof(CtrlRegDecoderTable)) + if (RegNo >= std::size(CtrlRegDecoderTable)) return MCDisassembler::Fail; static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); @@ -708,7 +708,7 @@ DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, /* 28 */ 0, 0, UTIMER, 0 }; - if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) + if (RegNo >= std::size(CtrlReg64DecoderTable)) return MCDisassembler::Fail; static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); @@ -862,7 +862,7 @@ DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31 }; - if (RegNo >= array_lengthof(GuestRegDecoderTable)) + if (RegNo >= std::size(GuestRegDecoderTable)) return MCDisassembler::Fail; if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister) return MCDisassembler::Fail; @@ -889,7 +889,7 @@ DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, /* 28 */ G29_28, 0, G31_30, 0 }; - if (RegNo >= array_lengthof(GuestReg64DecoderTable)) + if (RegNo >= std::size(GuestReg64DecoderTable)) return MCDisassembler::Fail; if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister) return MCDisassembler::Fail; diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h index 94129ee..7dacd87 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h @@ -97,7 +97,7 @@ public: { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 } }; - NumEntries = array_lengthof(Offsets); + NumEntries = std::size(Offsets); return Offsets; } diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index e10fcfe..7577720 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -998,8 +998,8 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI, static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 }; static const unsigned Regs1[] = { LC1, SA1 }; - auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01)) - : makeArrayRef(Regs1, array_lengthof(Regs1)); + auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, std::size(Regs01)) + : makeArrayRef(Regs1, std::size(Regs1)); for (unsigned R : CheckRegs) if (MI->modifiesRegister(R, TRI)) return true; diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index c7d4b72..d35100a 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -304,7 +304,7 @@ bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) { SDNode *S = StoreInstrForLoadIntrinsic(L, C); SDValue F[] = { SDValue(N,0), SDValue(N,1), SDValue(C,0), SDValue(C,1) }; SDValue T[] = { SDValue(L,0), SDValue(S,0), SDValue(L,1), SDValue(S,0) }; - ReplaceUses(F, T, array_lengthof(T)); + ReplaceUses(F, T, std::size(T)); // This transformation will leave the intrinsic dead. If it remains in // the DAG, the selection code will see it again, but without the load, // and it will generate a store that is normally required for it. diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index f2076a6..f9bd442 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -144,7 +144,7 @@ static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5 }; - const unsigned NumArgRegs = array_lengthof(ArgRegs); + const unsigned NumArgRegs = std::size(ArgRegs); unsigned RegNum = State.getFirstUnallocated(ArgRegs); // RegNum is an index into ArgRegs: skip a register if RegNum is odd. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 9c23577..65c9b9c 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -641,7 +641,7 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, Hexagon::fixup_Hexagon_GPREL16_0, Hexagon::fixup_Hexagon_GPREL16_1, Hexagon::fixup_Hexagon_GPREL16_2, Hexagon::fixup_Hexagon_GPREL16_3 }; - assert(Shift < array_lengthof(GPRelFixups)); + assert(Shift < std::size(GPRelFixups)); auto UsesGP = [] (const MCInstrDesc &D) { for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U) if (*U == Hexagon::GP) diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index bd28f54..85c7e52 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -1105,7 +1105,7 @@ static bool CC_LoongArch(const DataLayout &DL, LoongArchABI::ABI ABI, } // FPR32 and FPR64 alias each other. - if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) + if (State.getFirstUnallocated(ArgFPR32s) == std::size(ArgFPR32s)) UseGPRForFloat = true; if (UseGPRForFloat && ValVT == MVT::f32) { @@ -1130,7 +1130,7 @@ static bool CC_LoongArch(const DataLayout &DL, LoongArchABI::ABI ABI, DL.getTypeAllocSize(OrigTy) == TwoGRLenInBytes) { unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); // Skip 'odd' register if necessary. - if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) + if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1) State.AllocateReg(ArgGPRs); } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp index f321a90..6d9c93b 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp @@ -59,7 +59,7 @@ LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { // TODO: Add more fixup kinds. }; - static_assert((array_lengthof(Infos)) == LoongArch::NumTargetFixupKinds, + static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds, "Not all fixup kinds added to Infos array"); // Fixup kinds from .reloc directive are like R_LARCH_NONE. They diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp index 23af7d1..a667f45 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp @@ -81,9 +81,9 @@ public: {"fixup_8", 0, 8, 0}, {"fixup_sym_diff", 0, 32, 0}, }; - static_assert((array_lengthof(Infos)) == MSP430::NumTargetFixupKinds, + static_assert((std::size(Infos)) == MSP430::NumTargetFixupKinds, "Not all fixup kinds added to Infos array"); - + if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index 1484c6e..334ba26 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -458,12 +458,12 @@ static void AnalyzeArguments(CCState &State, static const MCPhysReg CRegList[] = { MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 }; - static const unsigned CNbRegs = array_lengthof(CRegList); + static const unsigned CNbRegs = std::size(CRegList); static const MCPhysReg BuiltinRegList[] = { MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 }; - static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList); + static const unsigned BuiltinNbRegs = std::size(BuiltinRegList); ArrayRef RegList; unsigned NbRegs; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 8050f9b..be577f6 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -429,7 +429,7 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_Mips_JALR", 0, 32, 0 }, { "fixup_MICROMIPS_JALR", 0, 32, 0 } }; - static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds, + static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS little endian fixup kinds added!"); const static MCFixupKindInfo BigEndianInfos[] = { @@ -508,7 +508,7 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_Mips_JALR", 0, 32, 0 }, { "fixup_MICROMIPS_JALR", 0, 32, 0 } }; - static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds, + static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS big endian fixup kinds added!"); if (Kind >= FirstLiteralRelocationKind) diff --git a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp index 78ffe00..73fd47d 100644 --- a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp @@ -246,7 +246,7 @@ bool Mips16TargetLowering::isEligibleForTailCallOptimization( } void Mips16TargetLowering::setMips16HardFloatLibCalls() { - for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) { + for (unsigned I = 0; I != std::size(HardFloatLibCalls); ++I) { assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) && "Array not sorted!"); if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL) diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp index 77cdf5c..cd67a09 100644 --- a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp +++ b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp @@ -37,7 +37,7 @@ static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, }; - const unsigned NumArgRegs = array_lengthof(ArgRegs); + const unsigned NumArgRegs = std::size(ArgRegs); unsigned RegNum = State.getFirstUnallocated(ArgRegs); @@ -62,7 +62,7 @@ static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128( PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, }; - const unsigned NumArgRegs = array_lengthof(ArgRegs); + const unsigned NumArgRegs = std::size(ArgRegs); unsigned RegNum = State.getFirstUnallocated(ArgRegs); int RegsLeft = NumArgRegs - RegNum; @@ -88,7 +88,7 @@ static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, PPC::F8 }; - const unsigned NumArgRegs = array_lengthof(ArgRegs); + const unsigned NumArgRegs = std::size(ArgRegs); unsigned RegNum = State.getFirstUnallocated(ArgRegs); diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index 0f70ec5..4138ea3 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -229,23 +229,23 @@ const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, CALLEE_SAVED_VRS}; if (Subtarget.is64BitELFABI()) { - NumEntries = array_lengthof(ELFOffsets64); + NumEntries = std::size(ELFOffsets64); return ELFOffsets64; } if (Subtarget.is32BitELFABI()) { - NumEntries = array_lengthof(ELFOffsets32); + NumEntries = std::size(ELFOffsets32); return ELFOffsets32; } assert(Subtarget.isAIXABI() && "Unexpected ABI."); if (Subtarget.isPPC64()) { - NumEntries = array_lengthof(AIXOffsets64); + NumEntries = std::size(AIXOffsets64); return AIXOffsets64; } - NumEntries = array_lengthof(AIXOffsets32); + NumEntries = std::size(AIXOffsets32); return AIXOffsets32; } diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 1015399..0366c08 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -4179,13 +4179,13 @@ SDValue PPCTargetLowering::LowerFormalArguments_32SVR4( PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, }; - const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); + const unsigned NumGPArgRegs = std::size(GPArgRegs); static const MCPhysReg FPArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8 }; - unsigned NumFPArgRegs = array_lengthof(FPArgRegs); + unsigned NumFPArgRegs = std::size(FPArgRegs); if (useSoftFloat() || hasSPE()) NumFPArgRegs = 0; @@ -4297,9 +4297,9 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4( PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 }; - const unsigned Num_GPR_Regs = array_lengthof(GPR); + const unsigned Num_GPR_Regs = std::size(GPR); const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13; - const unsigned Num_VR_Regs = array_lengthof(VR); + const unsigned Num_VR_Regs = std::size(VR); // Do a first pass over the arguments to determine whether the ABI // guarantees that our caller has allocated the parameter save area @@ -4757,9 +4757,9 @@ needStackSlotPassParameters(const PPCSubtarget &Subtarget, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 }; - const unsigned NumGPRs = array_lengthof(GPR); + const unsigned NumGPRs = std::size(GPR); const unsigned NumFPRs = 13; - const unsigned NumVRs = array_lengthof(VR); + const unsigned NumVRs = std::size(VR); const unsigned ParamAreaSize = NumGPRs * PtrByteSize; unsigned NumBytes = LinkageSize; @@ -6010,9 +6010,9 @@ SDValue PPCTargetLowering::LowerCall_64SVR4( PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 }; - const unsigned NumGPRs = array_lengthof(GPR); + const unsigned NumGPRs = std::size(GPR); const unsigned NumFPRs = useSoftFloat() ? 0 : 13; - const unsigned NumVRs = array_lengthof(VR); + const unsigned NumVRs = std::size(VR); // On ELFv2, we can avoid allocating the parameter area if all the arguments // can be passed to the callee in registers. @@ -7183,7 +7183,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX( static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10}; - const unsigned NumGPArgRegs = array_lengthof(IsPPC64 ? GPR_64 : GPR_32); + const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32); // The fixed integer arguments of a variadic function are stored to the // VarArgsFrameIndex on the stack so that they may be loaded by @@ -9396,7 +9396,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 }; - for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { + for (unsigned idx = 0; idx < std::size(SplatCsts); ++idx) { // Indirect through the SplatCsts array so that we favor 'vsplti -1' for // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' int i = SplatCsts[idx]; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index eb875b0..55f8b2b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -311,7 +311,7 @@ static const uint16_t FMAOpIdxInfo[][6] = { // Check if an opcode is a FMA instruction. If it is, return the index in array // FMAOpIdxInfo. Otherwise, return -1. int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const { - for (unsigned I = 0; I < array_lengthof(FMAOpIdxInfo); I++) + for (unsigned I = 0; I < std::size(FMAOpIdxInfo); I++) if (FMAOpIdxInfo[I][InfoArrayIdxFMAInst] == Opcode) return I; return -1; @@ -2332,7 +2332,7 @@ bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI, bool Found = false; for (const MachineOperand &MO : MI.operands()) { - for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) { + for (unsigned c = 0; c < std::size(RCs) && !Found; ++c) { const TargetRegisterClass *RC = RCs[c]; if (MO.isReg()) { if (MO.isDef() && RC->contains(MO.getReg())) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 96af23d..a1d7cf1 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -94,7 +94,7 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_riscv_set_6b", 2, 6, 0}, {"fixup_riscv_sub_6b", 2, 6, 0}, }; - static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds, + static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds, "Not all fixup kinds added to Infos array"); // Fixup kinds from .reloc directive are like R_RISCV_NONE. They diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2551860..8fd3570 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -10818,7 +10818,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, } // FPR16, FPR32, and FPR64 alias each other. - if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) { + if (State.getFirstUnallocated(ArgFPR32s) == std::size(ArgFPR32s)) { UseGPRForF16_F32 = true; UseGPRForF64 = true; } @@ -10847,7 +10847,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); // Skip 'odd' register if necessary. - if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) + if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1) State.AllocateReg(ArgGPRs); } diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index 1825b95..ef1f623 100644 --- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -226,7 +226,7 @@ static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder) { - if (RegNo >= array_lengthof(PRRegDecoderTable)) + if (RegNo >= std::size(PRRegDecoderTable)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); return MCDisassembler::Success; diff --git a/llvm/lib/Target/VE/VEFrameLowering.h b/llvm/lib/Target/VE/VEFrameLowering.h index 99eb411..36fc8b2 100644 --- a/llvm/lib/Target/VE/VEFrameLowering.h +++ b/llvm/lib/Target/VE/VEFrameLowering.h @@ -62,7 +62,7 @@ public: {VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128}, {VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160}, {VE::SX33, 168}}; - NumEntries = array_lengthof(Offsets); + NumEntries = std::size(Offsets); return Offsets; } diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 2742a75..a2a67fd 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -4264,7 +4264,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, } } - for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) { + for (unsigned I = 0, E = std::size(Match); I != E; ++I) { Tmp.back() = Suffixes[I]; if (MemOp && HasVectorReg) MemOp->Mem.Size = MemSize[I]; @@ -4310,7 +4310,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, if (NumSuccessfulMatches > 1) { char MatchChars[4]; unsigned NumMatches = 0; - for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) + for (unsigned I = 0, E = std::size(Match); I != E; ++I) if (Match[I] == Match_Success) MatchChars[NumMatches++] = Suffixes[I]; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 389207f..d31d175 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -12550,7 +12550,7 @@ static int canLowerByDroppingElements(ArrayRef Mask, bool MatchEven, continue; bool IsAnyViable = false; - for (unsigned j = 0; j != array_lengthof(ViableForN); ++j) + for (unsigned j = 0; j != std::size(ViableForN); ++j) if (ViableForN[j]) { uint64_t N = j + 1; @@ -12565,7 +12565,7 @@ static int canLowerByDroppingElements(ArrayRef Mask, bool MatchEven, break; } - for (unsigned j = 0; j != array_lengthof(ViableForN); ++j) + for (unsigned j = 0; j != std::size(ViableForN); ++j) if (ViableForN[j]) return j + 1; diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index 7585321..84b74c9 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -1345,11 +1345,11 @@ SDValue XCoreTargetLowering::LowerCCCArguments( }; XCoreFunctionInfo *XFI = MF.getInfo(); unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); - if (FirstVAReg < array_lengthof(ArgRegs)) { + if (FirstVAReg < std::size(ArgRegs)) { int offset = 0; // Save remaining registers, storing higher register numbers at a higher // address - for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { + for (int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { // Create a stack slot int FI = MFI.CreateFixedObject(4, offset, true); if (i == (int)FirstVAReg) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index b80064b..6bef15b 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -576,8 +576,7 @@ Value *FAddCombine::simplifyFAdd(AddendVect& Addends, unsigned InstrQuota) { } } - assert((NextTmpIdx <= array_lengthof(TmpResult) + 1) && - "out-of-bound access"); + assert((NextTmpIdx <= std::size(TmpResult) + 1) && "out-of-bound access"); Value *Result; if (!SimpVect.empty()) diff --git a/llvm/lib/Transforms/Utils/MetaRenamer.cpp b/llvm/lib/Transforms/Utils/MetaRenamer.cpp index 9fba2f3..0ea2106 100644 --- a/llvm/lib/Transforms/Utils/MetaRenamer.cpp +++ b/llvm/lib/Transforms/Utils/MetaRenamer.cpp @@ -87,7 +87,7 @@ struct Renamer { Renamer(unsigned int seed) { prng.srand(seed); } const char *newName() { - return metaNames[prng.rand() % array_lengthof(metaNames)]; + return metaNames[prng.rand() % std::size(metaNames)]; } PRNG prng; diff --git a/llvm/tools/llvm-objdump/COFFDump.cpp b/llvm/tools/llvm-objdump/COFFDump.cpp index 1fcbead..a1a4beb 100644 --- a/llvm/tools/llvm-objdump/COFFDump.cpp +++ b/llvm/tools/llvm-objdump/COFFDump.cpp @@ -173,7 +173,7 @@ void COFFDumper::printPEHeader(const PEHeader &Hdr) const { "Reserved", }; outs() << "\nThe Data Directory\n"; - for (uint32_t I = 0; I != array_lengthof(DirName); ++I) { + for (uint32_t I = 0; I != std::size(DirName); ++I) { uint32_t Addr = 0, Size = 0; if (const data_directory *Data = Obj.getDataDirectory(I)) { Addr = Data->RelativeVirtualAddress; diff --git a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp index 6bb91c0..fab99c8 100644 --- a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp +++ b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp @@ -906,8 +906,8 @@ void Decoder::decodeOpcodes(ArrayRef Opcodes, unsigned Offset, bool Terminated = false; for (unsigned OI = Offset, OE = Opcodes.size(); !Terminated && OI < OE; ) { for (unsigned DI = 0;; ++DI) { - if ((isAArch64 && (DI >= array_lengthof(Ring64))) || - (!isAArch64 && (DI >= array_lengthof(Ring)))) { + if ((isAArch64 && (DI >= std::size(Ring64))) || + (!isAArch64 && (DI >= std::size(Ring)))) { SW.startLine() << format("0x%02x ; Bad opcode!\n", Opcodes.data()[OI]); ++OI; diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp index 78594b1..305b23c 100644 --- a/llvm/tools/llvm-readobj/ELFDumper.cpp +++ b/llvm/tools/llvm-readobj/ELFDumper.cpp @@ -5064,7 +5064,7 @@ template static GNUAbiTag getGNUAbiTag(ArrayRef Desc) { "Linux", "Hurd", "Solaris", "FreeBSD", "NetBSD", "Syllable", "NaCl", }; StringRef OSName = "Unknown"; - if (Words[0] < array_lengthof(OSNames)) + if (Words[0] < std::size(OSNames)) OSName = OSNames[Words[0]]; uint32_t Major = Words[1], Minor = Words[2], Patch = Words[3]; std::string str; diff --git a/llvm/unittests/ADT/APFloatTest.cpp b/llvm/unittests/ADT/APFloatTest.cpp index a53eabe..3caa09f 100644 --- a/llvm/unittests/ADT/APFloatTest.cpp +++ b/llvm/unittests/ADT/APFloatTest.cpp @@ -937,13 +937,13 @@ TEST(APFloatTest, fromStringSpecials) { }; // Convert payload integer to decimal string representation. - std::string NaNPayloadDecStrings[array_lengthof(NaNPayloads)]; - for (size_t I = 0; I < array_lengthof(NaNPayloads); ++I) + std::string NaNPayloadDecStrings[std::size(NaNPayloads)]; + for (size_t I = 0; I < std::size(NaNPayloads); ++I) NaNPayloadDecStrings[I] = utostr(NaNPayloads[I]); // Convert payload integer to hexadecimal string representation. - std::string NaNPayloadHexStrings[array_lengthof(NaNPayloads)]; - for (size_t I = 0; I < array_lengthof(NaNPayloads); ++I) + std::string NaNPayloadHexStrings[std::size(NaNPayloads)]; + for (size_t I = 0; I < std::size(NaNPayloads); ++I) NaNPayloadHexStrings[I] = "0x" + utohexstr(NaNPayloads[I]); // Fix payloads to expected result. @@ -967,7 +967,7 @@ TEST(APFloatTest, fromStringSpecials) { for (char TypeChar : NaNTypes) { bool Signaling = (TypeChar == 's' || TypeChar == 'S'); - for (size_t J = 0; J < array_lengthof(NaNPayloads); ++J) { + for (size_t J = 0; J < std::size(NaNPayloads); ++J) { uint64_t Payload = (Signaling && !NaNPayloads[J]) ? SNaNDefaultPayload : NaNPayloads[J]; std::string &PayloadDec = NaNPayloadDecStrings[J]; @@ -2262,7 +2262,7 @@ TEST(APFloatTest, add) { { MSmallestNormalized, MSmallestNormalized, "-0x1p-125", APFloat::opOK, APFloat::fcNormal } }; - for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) { + for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) { APFloat x(SpecialCaseTests[i].x); APFloat y(SpecialCaseTests[i].y); APFloat::opStatus status = x.add(y, APFloat::rmNearestTiesToEven); @@ -2502,7 +2502,7 @@ TEST(APFloatTest, subtract) { { MSmallestNormalized, MSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero } }; - for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) { + for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) { APFloat x(SpecialCaseTests[i].x); APFloat y(SpecialCaseTests[i].y); APFloat::opStatus status = x.subtract(y, APFloat::rmNearestTiesToEven); @@ -2806,7 +2806,7 @@ TEST(APFloatTest, multiply) { APFloat::rmNearestTiesToAway}, }; - for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) { + for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) { APFloat x(SpecialCaseTests[i].x); APFloat y(SpecialCaseTests[i].y); APFloat::opStatus status = x.multiply(y, SpecialCaseTests[i].roundingMode); @@ -3088,7 +3088,7 @@ TEST(APFloatTest, divide) { APFloat::rmNearestTiesToAway}, }; - for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) { + for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) { APFloat x(SpecialCaseTests[i].x); APFloat y(SpecialCaseTests[i].y); APFloat::opStatus status = x.divide(y, SpecialCaseTests[i].roundingMode); @@ -4048,7 +4048,7 @@ TEST(APFloatTest, remainder) { { MVal6, MVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, }; - for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) { + for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) { APFloat x(SpecialCaseTests[i].x); APFloat y(SpecialCaseTests[i].y); APFloat::opStatus status = x.remainder(y); diff --git a/llvm/unittests/ADT/StringRefTest.cpp b/llvm/unittests/ADT/StringRefTest.cpp index 25cd3cd..719f7c6 100644 --- a/llvm/unittests/ADT/StringRefTest.cpp +++ b/llvm/unittests/ADT/StringRefTest.cpp @@ -664,7 +664,7 @@ TEST(StringRefTest, getAsInteger) { uint32_t U32; uint64_t U64; - for (size_t i = 0; i < array_lengthof(Unsigned); ++i) { + for (size_t i = 0; i < std::size(Unsigned); ++i) { bool U8Success = StringRef(Unsigned[i].Str).getAsInteger(0, U8); if (static_cast(Unsigned[i].Expected) == Unsigned[i].Expected) { ASSERT_FALSE(U8Success); @@ -696,7 +696,7 @@ TEST(StringRefTest, getAsInteger) { int32_t S32; int64_t S64; - for (size_t i = 0; i < array_lengthof(Signed); ++i) { + for (size_t i = 0; i < std::size(Signed); ++i) { bool S8Success = StringRef(Signed[i].Str).getAsInteger(0, S8); if (static_cast(Signed[i].Expected) == Signed[i].Expected) { ASSERT_FALSE(S8Success); @@ -742,7 +742,7 @@ static const char* BadStrings[] = { TEST(StringRefTest, getAsUnsignedIntegerBadStrings) { unsigned long long U64; - for (size_t i = 0; i < array_lengthof(BadStrings); ++i) { + for (size_t i = 0; i < std::size(BadStrings); ++i) { bool IsBadNumber = StringRef(BadStrings[i]).getAsInteger(0, U64); ASSERT_TRUE(IsBadNumber); } @@ -825,7 +825,7 @@ TEST(StringRefTest, consumeIntegerUnsigned) { uint32_t U32; uint64_t U64; - for (size_t i = 0; i < array_lengthof(ConsumeUnsigned); ++i) { + for (size_t i = 0; i < std::size(ConsumeUnsigned); ++i) { StringRef Str = ConsumeUnsigned[i].Str; bool U8Success = Str.consumeInteger(0, U8); if (static_cast(ConsumeUnsigned[i].Expected) == @@ -873,7 +873,7 @@ TEST(StringRefTest, consumeIntegerSigned) { int32_t S32; int64_t S64; - for (size_t i = 0; i < array_lengthof(ConsumeSigned); ++i) { + for (size_t i = 0; i < std::size(ConsumeSigned); ++i) { StringRef Str = ConsumeSigned[i].Str; bool S8Success = Str.consumeInteger(0, S8); if (static_cast(ConsumeSigned[i].Expected) == @@ -950,7 +950,7 @@ static const char join_result3[] = "a::b::c"; TEST(StringRefTest, joinStrings) { std::vector v1; std::vector v2; - for (size_t i = 0; i < array_lengthof(join_input); ++i) { + for (size_t i = 0; i < std::size(join_input); ++i) { v1.push_back(join_input[i]); v2.push_back(join_input[i]); } diff --git a/llvm/unittests/ADT/TinyPtrVectorTest.cpp b/llvm/unittests/ADT/TinyPtrVectorTest.cpp index a78f5b0..b3c03cb 100644 --- a/llvm/unittests/ADT/TinyPtrVectorTest.cpp +++ b/llvm/unittests/ADT/TinyPtrVectorTest.cpp @@ -45,7 +45,7 @@ protected: std::vector TestPtrs; TinyPtrVectorTest() { - for (size_t i = 0, e = array_lengthof(TestValues); i != e; ++i) + for (size_t i = 0, e = std::size(TestValues); i != e; ++i) TestPtrs.push_back(PtrT(&TestValues[i])); std::shuffle(TestPtrs.begin(), TestPtrs.end(), std::mt19937{}); diff --git a/llvm/unittests/ProfileData/CoverageMappingTest.cpp b/llvm/unittests/ProfileData/CoverageMappingTest.cpp index e04265e..2791f67 100644 --- a/llvm/unittests/ProfileData/CoverageMappingTest.cpp +++ b/llvm/unittests/ProfileData/CoverageMappingTest.cpp @@ -292,7 +292,7 @@ TEST_P(CoverageMappingTest, basic_write_read) { TEST_P(CoverageMappingTest, correct_deserialize_for_more_than_two_files) { const char *FileNames[] = {"bar", "baz", "foo"}; - static const unsigned N = array_lengthof(FileNames); + static const unsigned N = std::size(FileNames); startFunction("func", 0x1234); for (unsigned I = 0; I < N; ++I) @@ -321,7 +321,7 @@ TEST_P(CoverageMappingTest, load_coverage_for_more_than_two_files) { ProfileWriter.addRecord({"func", 0x1234, {0}}, Err); const char *FileNames[] = {"bar", "baz", "foo"}; - static const unsigned N = array_lengthof(FileNames); + static const unsigned N = std::size(FileNames); startFunction("func", 0x1234); for (unsigned I = 0; I < N; ++I) diff --git a/llvm/unittests/Support/BinaryStreamTest.cpp b/llvm/unittests/Support/BinaryStreamTest.cpp index 5c5f724..fdd29a7 100644 --- a/llvm/unittests/Support/BinaryStreamTest.cpp +++ b/llvm/unittests/Support/BinaryStreamTest.cpp @@ -103,7 +103,7 @@ private: }; constexpr endianness Endians[] = {big, little, native}; -constexpr uint32_t NumEndians = llvm::array_lengthof(Endians); +constexpr uint32_t NumEndians = std::size(Endians); constexpr uint32_t NumStreams = 2 * NumEndians; class BinaryStreamTest : public testing::Test { diff --git a/llvm/unittests/Support/CSKYTargetParserTest.cpp b/llvm/unittests/Support/CSKYTargetParserTest.cpp index 599e326..0cd53bc 100644 --- a/llvm/unittests/Support/CSKYTargetParserTest.cpp +++ b/llvm/unittests/Support/CSKYTargetParserTest.cpp @@ -1135,7 +1135,7 @@ TEST(TargetParserTest, CSKYArchExtFeature) { {"10e60", "no10e60", "+10e60", "-10e60"}, }; - for (unsigned i = 0; i < array_lengthof(ArchExt); i++) { + for (unsigned i = 0; i < std::size(ArchExt); i++) { EXPECT_EQ(StringRef(ArchExt[i][2]), CSKY::getArchExtFeature(ArchExt[i][0])); EXPECT_EQ(StringRef(ArchExt[i][3]), CSKY::getArchExtFeature(ArchExt[i][1])); } diff --git a/llvm/unittests/Support/CommandLineTest.cpp b/llvm/unittests/Support/CommandLineTest.cpp index 32dc440..41d483a 100644 --- a/llvm/unittests/Support/CommandLineTest.cpp +++ b/llvm/unittests/Support/CommandLineTest.cpp @@ -375,7 +375,7 @@ TEST(CommandLineTest, AliasesWithArguments) { { "-tool", "-alias", "x" } }; - for (size_t i = 0, e = array_lengthof(Inputs); i < e; ++i) { + for (size_t i = 0, e = std::size(Inputs); i < e; ++i) { StackOption Actual("actual"); StackOption Extra("extra"); StackOption Input(cl::Positional); @@ -404,8 +404,8 @@ void testAliasRequired(int argc, const char *const *argv) { TEST(CommandLineTest, AliasRequired) { const char *opts1[] = { "-tool", "-option=x" }; const char *opts2[] = { "-tool", "-o", "x" }; - testAliasRequired(array_lengthof(opts1), opts1); - testAliasRequired(array_lengthof(opts2), opts2); + testAliasRequired(std::size(opts1), opts1); + testAliasRequired(std::size(opts2), opts2); } TEST(CommandLineTest, HideUnrelatedOptions) { @@ -455,8 +455,8 @@ TEST(CommandLineTest, HideUnrelatedOptionsMulti) { TEST(CommandLineTest, SetMultiValues) { StackOption Option("option"); const char *args[] = {"prog", "-option=1", "-option=2"}; - EXPECT_TRUE(cl::ParseCommandLineOptions(array_lengthof(args), args, - StringRef(), &llvm::nulls())); + EXPECT_TRUE(cl::ParseCommandLineOptions(std::size(args), args, StringRef(), + &llvm::nulls())); EXPECT_EQ(Option, 2); } @@ -1032,8 +1032,8 @@ TEST(CommandLineTest, ResponseFileEOLs) { /*CurrentDir=*/StringRef(TestRoot), FS)); const char *Expected[] = {"clang", "-Xclang", "-Wno-whatever", nullptr, "input.cpp"}; - ASSERT_EQ(array_lengthof(Expected), Argv.size()); - for (size_t I = 0, E = array_lengthof(Expected); I < E; ++I) { + ASSERT_EQ(std::size(Expected), Argv.size()); + for (size_t I = 0, E = std::size(Expected); I < E; ++I) { if (Expected[I] == nullptr) { ASSERT_EQ(Argv[I], nullptr); } else { diff --git a/llvm/unittests/Support/FormatVariadicTest.cpp b/llvm/unittests/Support/FormatVariadicTest.cpp index 312b7b1..40c94b7 100644 --- a/llvm/unittests/Support/FormatVariadicTest.cpp +++ b/llvm/unittests/Support/FormatVariadicTest.cpp @@ -528,8 +528,7 @@ TEST(FormatVariadicTest, BigTest) { std::string S; llvm::raw_string_ostream Stream(S); - Stream << formatv(Intro, std::tuple_size::value, - llvm::array_lengthof(Ts)) + Stream << formatv(Intro, std::tuple_size::value, std::size(Ts)) << "\n"; Stream << formatv(Header, "Char", "HexInt", "Str", "Ref", "std::str", "double", "float", "pointer", "comma", "exp", "bigint", diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp index 8d8327e..883600c 100644 --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -736,7 +736,7 @@ TEST(TargetParserTest, ARMArchExtFeature) { {"mve", "nomve", "+mve", "-mve"}, {"mve.fp", "nomve.fp", "+mve.fp", "-mve.fp"}}; - for (unsigned i = 0; i < array_lengthof(ArchExt); i++) { + for (unsigned i = 0; i < std::size(ArchExt); i++) { EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0])); EXPECT_EQ(StringRef(ArchExt[i][3]), ARM::getArchExtFeature(ArchExt[i][1])); } @@ -767,7 +767,7 @@ TEST(TargetParserTest, ARMArchExtDependencies) { TEST(TargetParserTest, ARMparseHWDiv) { const char *hwdiv[] = {"thumb", "arm", "arm,thumb", "thumb,arm"}; - for (unsigned i = 0; i < array_lengthof(hwdiv); i++) + for (unsigned i = 0; i < std::size(hwdiv); i++) EXPECT_NE(ARM::AEK_INVALID, ARM::parseHWDiv((StringRef)hwdiv[i])); } @@ -785,7 +785,7 @@ TEST(TargetParserTest, ARMparseArchEndianAndISA) { "v8.7a", "v8.8-a", "v8.8a", "v8-r", "v8m.base", "v8m.main", "v8.1m.main"}; - for (unsigned i = 0; i < array_lengthof(Arch); i++) { + for (unsigned i = 0; i < std::size(Arch); i++) { std::string arm_1 = "armeb" + (std::string)(Arch[i]); std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb"; std::string arm_3 = "arm" + (std::string)(Arch[i]); @@ -824,7 +824,7 @@ TEST(TargetParserTest, ARMparseArchEndianAndISA) { } TEST(TargetParserTest, ARMparseArchProfile) { - for (unsigned i = 0; i < array_lengthof(ARMArch); i++) { + for (unsigned i = 0; i < std::size(ARMArch); i++) { switch (ARM::parseArch(ARMArch[i])) { case ARM::ArchKind::ARMV6M: case ARM::ArchKind::ARMV7M: @@ -864,7 +864,7 @@ TEST(TargetParserTest, ARMparseArchProfile) { } TEST(TargetParserTest, ARMparseArchVersion) { - for (unsigned i = 0; i < array_lengthof(ARMArch); i++) + for (unsigned i = 0; i < std::size(ARMArch); i++) if (((std::string)ARMArch[i]).substr(0, 4) == "armv") EXPECT_EQ((ARMArch[i][4] - 48u), ARM::parseArchVersion(ARMArch[i])); else @@ -1585,7 +1585,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"pmuv3", "nopmuv3", "+perfmon", "-perfmon"}, }; - for (unsigned i = 0; i < array_lengthof(ArchExt); i++) { + for (unsigned i = 0; i < std::size(ArchExt); i++) { EXPECT_EQ(StringRef(ArchExt[i][2]), AArch64::getArchExtFeature(ArchExt[i][0])); EXPECT_EQ(StringRef(ArchExt[i][3]), diff --git a/llvm/utils/KillTheDoctor/KillTheDoctor.cpp b/llvm/utils/KillTheDoctor/KillTheDoctor.cpp index 358ef16..4f642f8 100644 --- a/llvm/utils/KillTheDoctor/KillTheDoctor.cpp +++ b/llvm/utils/KillTheDoctor/KillTheDoctor.cpp @@ -204,10 +204,8 @@ static std::error_code GetFileNameFromHandle(HANDLE FileHandle, if (!MappedFile) return windows_error(::GetLastError()); - Success = ::GetMappedFileNameA(::GetCurrentProcess(), - MappedFile, - Filename, - array_lengthof(Filename) - 1); + Success = ::GetMappedFileNameA(::GetCurrentProcess(), MappedFile, Filename, + std::size(Filename) - 1); if (!Success) return windows_error(::GetLastError()); @@ -239,15 +237,11 @@ static std::string FindProgram(const std::string &Program, LPCSTR Extension = NULL; if (ext.size() && ext[0] == '.') Extension = ext.c_str(); - DWORD length = ::SearchPathA(NULL, - Program.c_str(), - Extension, - array_lengthof(PathName), - PathName, - NULL); + DWORD length = ::SearchPathA(NULL, Program.c_str(), Extension, + std::size(PathName), PathName, NULL); if (length == 0) ec = windows_error(::GetLastError()); - else if (length > array_lengthof(PathName)) { + else if (length > std::size(PathName)) { // This may have been the file, return with error. ec = windows_error(ERROR_BUFFER_OVERFLOW); break; diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp index 1d73827..6615796 100644 --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -1180,7 +1180,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { O.indent(2) << " makeArrayRef(OpToPatterns),\n"; O.indent(2) << " makeArrayRef(Patterns),\n"; O.indent(2) << " makeArrayRef(Conds),\n"; - O.indent(2) << " StringRef(AsmStrings, array_lengthof(AsmStrings)),\n"; + O.indent(2) << " StringRef(AsmStrings, std::size(AsmStrings)),\n"; if (MCOpPredicates.empty()) O.indent(2) << " nullptr,\n"; else diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp index 0962f7c..a2da508 100644 --- a/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/CodeGenTarget.cpp @@ -482,7 +482,7 @@ static const char *FixedInstrs[] = { nullptr}; unsigned CodeGenTarget::getNumFixedInstructions() { - return array_lengthof(FixedInstrs) - 1; + return std::size(FixedInstrs) - 1; } /// Return all of the instructions defined by the target, ordered by diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 2f7d85f..f6ae647f 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -440,7 +440,7 @@ void RegisterInfoEmitter::EmitRegMappingTables( OS << "extern const unsigned " << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize"; if (!isCtor) - OS << " = array_lengthof(" << Namespace + OS << " = std::size(" << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n"; else OS << ";\n\n"; @@ -498,7 +498,7 @@ void RegisterInfoEmitter::EmitRegMappingTables( OS << "extern const unsigned " << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; if (!isCtor) - OS << " = array_lengthof(" << Namespace + OS << " = std::size(" << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; else OS << ";\n\n"; diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 1f3ab48..435301e 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -653,7 +653,7 @@ static const char* stringForDecisionType(ModRMDecisionType dt) { } DisassemblerTables::DisassemblerTables() { - for (unsigned i = 0; i < llvm::array_lengthof(Tables); i++) + for (unsigned i = 0; i < std::size(Tables); i++) Tables[i] = std::make_unique(); HasConflicts = false; -- 2.7.4