From 5e8b12ffbb8c685ee7ee7da1e3d93836c645d671 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 12 Sep 2014 14:06:50 +0100 Subject: [PATCH] target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 Implement debug registers DBGVCR, OSDLR_EL1 and MDCCSR_EL0 (as dummy or limited-functionality). 32 bit Linux kernels will access these at startup so they are required for breakpoints and watchpoints to be supported. Signed-off-by: Peter Maydell --- target-arm/helper.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index fc6a6f8..d2e741a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2250,10 +2250,29 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue = 0 }, + /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. + * We don't implement the configurable EL0 access. + */ + { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, + .type = ARM_CP_NO_MIGRATE, + .access = PL1_R, + .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), + .resetfn = arm_cp_reset_ignore }, /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, .access = PL1_W, .type = ARM_CP_NOP }, + /* Dummy OSDLR_EL1: 32-bit Linux will read this */ + { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, + .access = PL1_RW, .type = ARM_CP_NOP }, + /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't + * implement vector catch debug events yet. + */ + { .name = "DBGVCR", + .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_NOP }, REGINFO_SENTINEL }; -- 2.7.4