From 5e78b749eccf0aa57433b177103420103d4e13ec Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Mon, 13 Feb 2023 21:28:50 -0800 Subject: [PATCH] [ARM] Use llvm::rotl and llvm::rotr (NFC) --- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- .../Target/ARM/Disassembler/ARMDisassembler.cpp | 2 +- .../Target/ARM/MCTargetDesc/ARMAddressingModes.h | 44 ++++++++-------------- .../lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp | 2 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 4 +- 6 files changed, 22 insertions(+), 36 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index f1ba015..1cf6de7 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2499,7 +2499,7 @@ void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, while (NumBytes) { unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); - unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); + unsigned ThisVal = NumBytes & llvm::rotr(0xFF, RotAmt); assert(ThisVal && "Didn't extract field correctly"); // We will handle these bits from offset, clear them. @@ -2680,7 +2680,7 @@ bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, // Otherwise, pull as much of the immedidate into this ADDri/SUBri // as possible. unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); - unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); + unsigned ThisImmVal = Offset & llvm::rotr(0xFF, RotAmt); // We will handle these bits from offset, clear them. Offset &= ~ThisImmVal; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 2586dd4..75733a9 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8798,7 +8798,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst, // before passing it to the ADR instruction. unsigned Enc = Inst.getOperand(2).getImm(); TmpInst.addOperand(MCOperand::createImm( - ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); + llvm::rotr(Enc & 0xFF, (Enc & 0xF00) >> 7))); } else { // Turn PC-relative expression into absolute expression. // Reading PC provides the start of the current instruction + 8 and diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 597eba2..38c291c 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4910,7 +4910,7 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, } else { unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; unsigned rot = fieldFromInstruction(Val, 7, 5); - unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); + unsigned imm = llvm::rotr(unrot, rot); Inst.addOperand(MCOperand::createImm(imm)); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h index 3170d2a..163360c 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h @@ -81,20 +81,6 @@ namespace ARM_AM { } } - /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. - /// - inline unsigned rotr32(unsigned Val, unsigned Amt) { - assert(Amt < 32 && "Invalid rotate amount"); - return (Val >> Amt) | (Val << ((32-Amt)&31)); - } - - /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. - /// - inline unsigned rotl32(unsigned Val, unsigned Amt) { - assert(Amt < 32 && "Invalid rotate amount"); - return (Val << Amt) | (Val >> ((32-Amt)&31)); - } - //===--------------------------------------------------------------------===// // Addressing Mode #1: shift_operand with registers //===--------------------------------------------------------------------===// @@ -139,7 +125,7 @@ namespace ARM_AM { unsigned RotAmt = TZ & ~1; // If we can handle this spread, return it. - if ((rotr32(Imm, RotAmt) & ~255U) == 0) + if ((llvm::rotr(Imm, RotAmt) & ~255U) == 0) return (32-RotAmt)&31; // HW rotates right, not left. // For values like 0xF000000F, we should ignore the low 6 bits, then @@ -147,7 +133,7 @@ namespace ARM_AM { if (Imm & 63U) { unsigned TZ2 = llvm::countr_zero(Imm & ~63U); unsigned RotAmt2 = TZ2 & ~1; - if ((rotr32(Imm, RotAmt2) & ~255U) == 0) + if ((llvm::rotr(Imm, RotAmt2) & ~255U) == 0) return (32-RotAmt2)&31; // HW rotates right, not left. } @@ -168,40 +154,40 @@ namespace ARM_AM { unsigned RotAmt = getSOImmValRotate(Arg); // If this cannot be handled with a single shifter_op, bail out. - if (rotr32(~255U, RotAmt) & Arg) + if (llvm::rotr(~255U, RotAmt) & Arg) return -1; // Encode this correctly. - return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); + return llvm::rotl(Arg, RotAmt) | ((RotAmt >> 1) << 8); } /// isSOImmTwoPartVal - Return true if the specified value can be obtained by /// or'ing together two SOImmVal's. inline bool isSOImmTwoPartVal(unsigned V) { // If this can be handled with a single shifter_op, bail out. - V = rotr32(~255U, getSOImmValRotate(V)) & V; + V = llvm::rotr(~255U, getSOImmValRotate(V)) & V; if (V == 0) return false; // If this can be handled with two shifter_op's, accept. - V = rotr32(~255U, getSOImmValRotate(V)) & V; + V = llvm::rotr(~255U, getSOImmValRotate(V)) & V; return V == 0; } /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, /// return the first chunk of it. inline unsigned getSOImmTwoPartFirst(unsigned V) { - return rotr32(255U, getSOImmValRotate(V)) & V; + return llvm::rotr(255U, getSOImmValRotate(V)) & V; } /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, /// return the second chunk of it. inline unsigned getSOImmTwoPartSecond(unsigned V) { // Mask out the first hunk. - V = rotr32(~255U, getSOImmValRotate(V)) & V; + V = llvm::rotr(~255U, getSOImmValRotate(V)) & V; // Take what's left. - assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); + assert(V == (llvm::rotr(255U, getSOImmValRotate(V)) & V)); return V; } @@ -216,7 +202,7 @@ namespace ARM_AM { // Return false if ~(-First) is not a SoImmval. First = getSOImmTwoPartFirst(-V); First = ~(-First); - return !(rotr32(~255U, getSOImmValRotate(First)) & First); + return !(llvm::rotr(~255U, getSOImmValRotate(First)) & First); } /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed @@ -307,8 +293,9 @@ namespace ARM_AM { return -1; // If 'Arg' can be handled with a single shifter_op return the value. - if ((rotr32(0xff000000U, RotAmt) & V) == V) - return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); + if ((llvm::rotr(0xff000000U, RotAmt) & V) == V) + return (llvm::rotr(V, 24 - RotAmt) & 0x7f) | + ((RotAmt + 8) << 7); return -1; } @@ -345,7 +332,7 @@ namespace ARM_AM { // out. Those should be handled directly, not with a two-part val. if (getT2SOImmValSplatVal(V) != -1) return false; - V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; + V = llvm::rotr(~255U, getT2SOImmValRotate(V)) & V; if (V == 0) return false; @@ -369,7 +356,7 @@ namespace ARM_AM { assert (isT2SOImmTwoPartVal(Imm) && "Immedate cannot be encoded as two part immediate!"); // Try a shifter operand as one part - unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm; + unsigned V = llvm::rotr(~255, getT2SOImmValRotate(Imm)) & Imm; // If the rest is encodable as an immediate, then return it. if (getT2SOImmVal(V) != -1) return V; @@ -759,4 +746,3 @@ namespace ARM_AM { } // end namespace llvm #endif - diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp index 1ada656..737c373 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp @@ -1386,7 +1386,7 @@ void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum, break; } - int32_t Rotated = ARM_AM::rotr32(Bits, Rot); + int32_t Rotated = llvm::rotr(Bits, Rot); if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) { // #rot has the least possible value O << "#" << markup("(0xff000000U, RotAmt); NumBytes &= ~ThisVal; assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); @@ -604,7 +604,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, // Otherwise, extract 8 adjacent bits from the immediate into this // t2ADDri/t2SUBri. unsigned RotAmt = llvm::countl_zero(Offset); - unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); + unsigned ThisImmVal = Offset & llvm::rotr(0xff000000U, RotAmt); // We will handle these bits from offset, clear them. Offset &= ~ThisImmVal; -- 2.7.4