From 5e46ad83db102ce36ec4d47a62e115b7ac812311 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:39 +0200 Subject: [PATCH] drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start While it's not very well understood, there is some sort of a fault handler implemented in the GMU firmware which triggers when a certain bit is set, resulting in the M3 core not booting up the way we expect it to. Write a magic value to a magic register to hopefully prevent that from happening. Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/543335/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index bf7f855..452beb9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -791,6 +791,12 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) (1 << 31) | (0xa << 18) | (0xa0)); /* + * Snapshots toggle the NMI bit which will result in a jump to the NMI + * handler instead of __main. Set the M3 config value to avoid that. + */ + gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); + + /* * Note that the GMU has a slightly different layout for * chip_id, for whatever reason, so a bit of massaging * is needed. The upper 16b are the same, but minor and -- 2.7.4