From 5e31dd2650ebb39c206780c900035e4eb64b6957 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Wed, 19 Aug 2020 12:07:28 -0400
Subject: [PATCH] [InstCombine] avoid 'tmp' names in tests; NFC

They may conflict with update_test_checks.py regexes.
---
 .../Transforms/InstCombine/2010-11-01-lshr-mask.ll | 88 +++++++++++-----------
 1 file changed, 44 insertions(+), 44 deletions(-)

diff --git a/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll b/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
index 169bf70..7d75e16 100644
--- a/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
+++ b/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
@@ -1,57 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -instcombine -instcombine-infinite-loop-threshold=2 -S < %s | FileCheck %s
 
 ; <rdar://problem/8606771>
 define i32 @main(i32 %argc) {
 ; CHECK-LABEL: @main(
-; CHECK-NEXT:    [[TMP3151:%.*]] = trunc i32 %argc to i8
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i8 [[TMP3151]], 5
-; CHECK-NEXT:    [[TMP4126:%.*]] = and i8 [[TMP1]], 64
-; CHECK-NEXT:    [[TMP4127:%.*]] = xor i8 [[TMP4126]], 64
-; CHECK-NEXT:    [[TMP4086:%.*]] = zext i8 [[TMP4127]] to i32
-; CHECK-NEXT:    ret i32 [[TMP4086]]
+; CHECK-NEXT:    [[T3151:%.*]] = trunc i32 [[ARGC:%.*]] to i8
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i8 [[T3151]], 5
+; CHECK-NEXT:    [[T4126:%.*]] = and i8 [[TMP1]], 64
+; CHECK-NEXT:    [[T4127:%.*]] = xor i8 [[T4126]], 64
+; CHECK-NEXT:    [[T4086:%.*]] = zext i8 [[T4127]] to i32
+; CHECK-NEXT:    ret i32 [[T4086]]
 ;
-  %tmp3151 = trunc i32 %argc to i8
-  %tmp3161 = or i8 %tmp3151, -17
-  %tmp3162 = and i8 %tmp3151, 122
-  %tmp3163 = xor i8 %tmp3162, -17
-  %tmp4114 = shl i8 %tmp3163, 6
-  %tmp4115 = xor i8 %tmp4114, %tmp3163
-  %tmp4120 = xor i8 %tmp3161, %tmp4115
-  %tmp4126 = lshr i8 %tmp4120, 7
-  %tmp4127 = mul i8 %tmp4126, 64
-  %tmp4086 = zext i8 %tmp4127 to i32
-  ret i32 %tmp4086
+  %t3151 = trunc i32 %argc to i8
+  %t3161 = or i8 %t3151, -17
+  %t3162 = and i8 %t3151, 122
+  %t3163 = xor i8 %t3162, -17
+  %t4114 = shl i8 %t3163, 6
+  %t4115 = xor i8 %t4114, %t3163
+  %t4120 = xor i8 %t3161, %t4115
+  %t4126 = lshr i8 %t4120, 7
+  %t4127 = mul i8 %t4126, 64
+  %t4086 = zext i8 %t4127 to i32
+  ret i32 %t4086
 }
 
 ; rdar://8739316
 define i8 @foo(i8 %arg, i8 %arg1) {
 ; CHECK-LABEL: @foo(
-; CHECK-NEXT:    [[TMP:%.*]] = shl i8 %arg, 7
-; CHECK-NEXT:    [[TMP2:%.*]] = and i8 %arg1, 84
-; CHECK-NEXT:    [[TMP3:%.*]] = and i8 %arg1, -118
-; CHECK-NEXT:    [[TMP4:%.*]] = and i8 %arg1, 33
-; CHECK-NEXT:    [[TMP5:%.*]] = sub nsw i8 40, [[TMP2]]
-; CHECK-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 84
-; CHECK-NEXT:    [[TMP7:%.*]] = or i8 [[TMP4]], [[TMP6]]
-; CHECK-NEXT:    [[TMP8:%.*]] = xor i8 [[TMP]], [[TMP3]]
-; CHECK-NEXT:    [[TMP9:%.*]] = or i8 [[TMP7]], [[TMP8]]
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i8 [[TMP8]], 7
-; CHECK-NEXT:    [[TMP11:%.*]] = shl nuw nsw i8 [[TMP10]], 5
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i8 [[TMP11]], [[TMP9]]
-; CHECK-NEXT:    ret i8 [[TMP12]]
+; CHECK-NEXT:    [[T:%.*]] = shl i8 [[ARG:%.*]], 7
+; CHECK-NEXT:    [[T2:%.*]] = and i8 [[ARG1:%.*]], 84
+; CHECK-NEXT:    [[T3:%.*]] = and i8 [[ARG1]], -118
+; CHECK-NEXT:    [[T4:%.*]] = and i8 [[ARG1]], 33
+; CHECK-NEXT:    [[T5:%.*]] = sub nsw i8 40, [[T2]]
+; CHECK-NEXT:    [[T6:%.*]] = and i8 [[T5]], 84
+; CHECK-NEXT:    [[T7:%.*]] = or i8 [[T4]], [[T6]]
+; CHECK-NEXT:    [[T8:%.*]] = xor i8 [[T]], [[T3]]
+; CHECK-NEXT:    [[T9:%.*]] = or i8 [[T7]], [[T8]]
+; CHECK-NEXT:    [[T10:%.*]] = lshr i8 [[T8]], 7
+; CHECK-NEXT:    [[T11:%.*]] = shl nuw nsw i8 [[T10]], 5
+; CHECK-NEXT:    [[T12:%.*]] = xor i8 [[T11]], [[T9]]
+; CHECK-NEXT:    ret i8 [[T12]]
 ;
-  %tmp = shl i8 %arg, 7
-  %tmp2 = and i8 %arg1, 84
-  %tmp3 = and i8 %arg1, -118
-  %tmp4 = and i8 %arg1, 33
-  %tmp5 = sub i8 -88, %tmp2
-  %tmp6 = and i8 %tmp5, 84
-  %tmp7 = or i8 %tmp4, %tmp6
-  %tmp8 = xor i8 %tmp, %tmp3
-  %tmp9 = or i8 %tmp7, %tmp8
-  %tmp10 = lshr i8 %tmp8, 7
-  %tmp11 = shl i8 %tmp10, 5
-  %tmp12 = xor i8 %tmp11, %tmp9
-  ret i8 %tmp12
+  %t = shl i8 %arg, 7
+  %t2 = and i8 %arg1, 84
+  %t3 = and i8 %arg1, -118
+  %t4 = and i8 %arg1, 33
+  %t5 = sub i8 -88, %t2
+  %t6 = and i8 %t5, 84
+  %t7 = or i8 %t4, %t6
+  %t8 = xor i8 %t, %t3
+  %t9 = or i8 %t7, %t8
+  %t10 = lshr i8 %t8, 7
+  %t11 = shl i8 %t10, 5
+  %t12 = xor i8 %t11, %t9
+  ret i8 %t12
 }
-
-- 
2.7.4