From 5e079577e12e4b709639f5a92bcbd3e04c93052b Mon Sep 17 00:00:00 2001
From: Colin LeMahieu <colinl@codeaurora.org>
Date: Mon, 5 Jan 2015 18:08:21 +0000
Subject: [PATCH] [Hexagon] Adding round reg/imm and bitsplit instructions.

llvm-svn: 225188
---
 llvm/lib/Target/Hexagon/HexagonInstrInfo.td     |  7 +++++++
 llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td   | 14 ++++++++++++++
 llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt |  6 ++++++
 llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt |  2 ++
 4 files changed, 29 insertions(+)

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index d73adc6..7ce65f3 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -3220,6 +3220,13 @@ class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
     let Inst{7-5} = MinOp;
     let Inst{4-0} = dst;
   }
+
+class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
+  : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
+
+let hasNewValue = 1 in
+class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
+  : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
   
 let hasNewValue = 1 in
 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
index 07892ed..6892b5c 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -1747,6 +1747,20 @@ def M4_xor_xacc
     let Inst{12-8}  = Rtt;
     let Inst{4-0}   = Rxx;
   }
+  
+// Split bitfield
+let isCodeGenOnly = 0 in
+def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
+
+// Arithmetic/Convergent round
+let isCodeGenOnly = 0 in
+def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
+
+let isCodeGenOnly = 0 in
+def A4_round_ri  : T_S2op_2_ii <"round", 0b111, 0b100>;
+
+let Defs = [USR_OVF], isCodeGenOnly = 0 in
+def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
 
 //  Add and accumulate.
 //  Rd=add(Rs,add(Ru,#s6))
diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt
index ec9944bd..d614e9c 100644
--- a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt
+++ b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt
@@ -86,6 +86,12 @@
 # CHECK: r17:16 = neg(r21:20)
 0xd1 0xc0 0x95 0x8c
 # CHECK: r17 = neg(r21):sat
+0x11 0xdf 0xf5 0x8c
+# CHECK: r17 = cround(r21, #31)
+0x91 0xdf 0xf5 0x8c
+# CHECK: r17 = round(r21, #31)
+0xd1 0xdf 0xf5 0x8c
+# CHECK: r17 = round(r21, #31):sat
 0x71 0xd5 0x1f 0xef
 # CHECK: r17 += sub(r21, r31)
 0x11 0xd5 0x3f 0xd5
diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt
index 601b3e1..ac670c0 100644
--- a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt
+++ b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt
@@ -64,6 +64,8 @@
 # CHECK: r17 = clrbit(r21, r31)
 0x91 0xdf 0x95 0xc6
 # CHECK: r17 = togglebit(r21, r31)
+0x90 0xdf 0xd5 0x88
+# CHECK: r17:16 = bitsplit(r21, #31)
 0xf1 0xcd 0x15 0x87
 # CHECK: r17 = tableidxb(r21, #7, #13):raw
 0xf1 0xcd 0x55 0x87
-- 
2.7.4